- Scenario-Based Network Design for P1687
Farrokh Ghani Zadegan, Gunnar Carlsson, Erik Larsson
The 12th Swedish System-on-Chip Conference (SSoCC 2013), Ystad, Sweden, May 6-7, 2013 (not reviewed, not printed).
- An MPSoCs Demonstrator for Fault Injection and Fault Handling in an IEEE P1687 Environment
Kim Petersen, Dimitar Nikolov, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
IEEE 17th European Test Symposimu (ETS 2012), Annecy, France, May 28-June 1, 2012.
- Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
5th Workshop on Dependable and Secure Nanocomputing (WSDN 2011), Hong Kong, June 27, 2011.
- Study on the Level of Confidence for Roll-back Recovery with Checkpointing
Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011), Trondheim, Norway, May 26-27, 2011.
- A Study of Instrument Reuse and Retargeting in P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Erik Larsson, Gunnar Carlsson
IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011.
- Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
Breeta SenGupta, Urban Ingelsson, Erik Larsson
25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012.
- Test Planning for Core-based 3D Stacked ICs under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012.
- Test Planning for 3D Stacked ICs with Through-Silicon Vias
Breeta SenGupta, Urban Ingelsson, Erik Larsson
2nd IEEE Intl. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Anaheim, CA, USA, September 22-23, 2011.
- Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Erik Larsson, Gunnar Carlsson
IEEE Design & Test of Computers, Apr. 2012, Volume 29, Issue 2, pp. 79-88.
- Testing advanced electronics systems (One-day Tutorial)
Erik Larsson
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010), Malaysia, December 2010.
- Power-Aware SOC Test Planning (Keynote)
Erik Larsson
Workshop on RTL and High Level Testing (WRTLT 2008), Sapporo, Japan, November 2008.
- Manufacturing Test Solutions for System-On-Chip Integrated Circuits (One-day Tutorial)
Erik Larsson, Krishnendu Chakrabarty
VLSI Design and Test Symposium (VDAT 2007), Kolkata, India, August 2007.
- Conference Reports - ETS 2011: European Test Symposium
Erik Larsson
IEEE Design & Test of Computers, Volume: 28, Issue: 5, September-October 2011, ISSN: 0740-7475, pp. 95.
- Access Time Analysis for IEEE P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
IEEE Transactions on Computers, Oct. 2012, Volume 61, Issue 10, pp 1459-1472.
- Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
Farrokh Ghani Zadegan, Urban Ingelsson, Golnaz Asani, Gunnar Carlsson, Erik Larsson
20th IEEE Asian Test Symposium (ATS 2011), New Delhi, India, November 21-23, 2011.
- Test Scheduling with Constraints for IEEE P1687 (poster)
Golnaz Asani, Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
International Test Conference (ITC 2011), Anaheim, CA, USA, September 18-23, 2011.
- Scheduling Tests for 3D Stacked Chips under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
Journal of Electronic Testing: Theory and Applications (JETTA), Feb. 2012, Volume 28, Issue 1, pp. 121-135.
- Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
Pramod Subramanyan, Virendra Singh, Kewal Saluja, Erik Larsson
XXIX IEEE International Conference on Computer Design (ICCD 2011), Massachusetts, USA, October 9-12, 2011.
- Conference Reports - RASDAT 2011: Workshop on Reliability Aware System Design and Test
Erik Larsson
IEEE Design & Test of Computers, Volume: 28, Issue: 3, May-June 2011, pp. 82-83.
- Conference Reports - RASDAT 2010: Workshop on Reliability Aware System Design and Test
Erik Larsson
IEEE Design & Test of Computers, Volume: 27, Issue: 5, Sept.-Oct. 2010, pp. 72-73.
- European Test Symposium (ETS) 2011
Erik Larsson, Einar Aas
Elektronikk - tidsskrift for IT och telekom, pp. 33, April 2011.
- Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster)
Breeta SenGupta, Urban Ingelsson, Erik Larsson
European Test Symposium (ETS 2011), Trondheim, Norway, May 23-27, 2011.
- Automated Design for IEEE P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
- Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Breeta SenGupta, Urban Ingelsson, Erik Larsson
The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
- Level of Confidence Study for Roll-back Recovery with Checkpointing
Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
- Cost Reduction of Wear-Out Monitoring by Measurement Point Selection
Urban Ingelsson, Shih-Yen Chang, Erik Larsson
The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
- SoC-Level Fault Management based on P1687 IJTAG
Gunnar Carlsson, Artur Jutman, Erik Larsson
Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 14-18, 2011.
- Measurement Point Selection for In-Operation Wear-Out Monitoring
Urban Ingelsson, Shih-Yen Chang, Erik Larsson
14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011.
- Test Scheduling for 3D Stacked ICs under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011.
- Test scheduling on IJTAG
Erik Larsson, Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson
Nordic Test Forum (NTF 2010), Drammen, Norway, November 23-24, 2010.
- Design Automation for IEEE P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 14-18, 2011.
- Power Constrained Test Scheduling for 3D Stacked Chips (poster)
Breeta SenGupta, Urban Ingelsson, Erik Larsson
1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA, November 4-5, 2010.
- Scheduling Tests for 3D Stacked Chips Under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011.
- Optimizing Fault Tolerance for Multi-Processor System-on-Chip
Dimitar Nikolov, Mikael Väyrynen, Urban Ingelsson, Erik Larsson, Virendra Singh
Book Chapter in "Design and Test Technology for Dependable Systems-on-chip", Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, ISBN: 978-1-6096-0212-3, 2010.
- Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
Anders Larsson, Urban Ingelsson, Erik Larsson, Krishnendu Chakrabarty
Book Chapter in "Design and Test Technology for Dependable Systems-on-chip", Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, ISBN: 978-1-6096-0212-3, 2010.
- Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
Vinay N.S., Indira Rawat, M.S. Gaur, Erik Larsson, Virendra Singh
IEEE East-West Design & Test Symposium (EWDTS10), St. Petersburg, Russia, September 17-20, 2010.
- Efficient Embedding of Deterministic Test Data
Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.
- Test Time Analysis for IEEE P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.
- Test Scheduling of Modular System-on-Chip under Capture Power Constraint
Jaynarayan Tudu, Erik Larsson, Virendra Singh
Workshop on RTL ATPG & DFT (WRTLT10), Shanghai, China, December 2010.
- Checking Pipelined Distributed Global Properties for Post-silicon Debug
Erik Larsson, Bart Vermeulen, Kees Goossens
Workshop on RTL ATPG & DFT (WRTLT10), Shanghai, China, December 2010.
- Efficient Embedding of Deterministic Test Data
Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
- Scheduling Tests for Stacked 3D Chips under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
- Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Singh, Erik Larsson
Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
- Checking Pipelined Distributed and Global Properties at Post-silicon Debug
Erik Larsson, Bart Vermeulen, Kees Goossens
DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10) , Anaheim, CA, USA, June 13-18, 2010.
- Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10), Fairmont Chicago, Millennium Park, Chicago, Illinois, USA, June 28-July 1, 2010, pp. 121-130.
- Energy-Efficient Redundant Execution for Chip Multiprocessors
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
Great Lakes Symposium on VLSI on (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010, pp. 143-146.
- A Distributed Architecture to Check Global Properties for Post-Silicon Debug
Erik Larsson, Bart Vermeulen, Kees Goossens
IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.
- Scan Cells Reordering to Minimize Peak Power During Test Cycle: A Graph Theoretic Approach
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.
- Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
Great Lakes Symposium on VLSI (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010, pp. 73-78.
- On-line Techniques to Adjust and Optimize Checkpointing Frequency
Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010, pp. 29-33.
- Multiplexed Redundant Execution: A Technique for Efficient Fault Tolerance in Chip Multiprocessors
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
Design Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010, pp. 1572-1577.
- Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
5th IEEE Intl. Symposium on Electronic Design, Test & Applications (DELTA 2010), Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 281-285.
- Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), Hongkong, China, November 27-28, 2009, pp. 43-48.
- An Even-Odd DFD Technique for Scan Chain Diagnosis
Venkat Rajesh, Erik Larsson, Manoj S. Gaur, Virendra Singh
Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November 27-28, 2009.
- On Scan Chain Diagnosis for Intermittent Faults
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson
IEEE Asian Test Symposium (ATS), Taichung, Taiwan, November 23-26, 2009, pp. 47-54.
- Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, Virendra Singh
7th IEEE East-West Design & Test Symposium (EWDTS), Moscow, Russia, September 18-21, 2009, pp. 1-4.
- Power Efficient Redundant Execution for Chip Multiprocessors
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June 29, 2009, Paper 9, pp. 1-6.
- Deterministic Scan-Chain Diagnosis for Intermittent Faults
Dan Adolfsson, Joanna Siew, Erik Larsson, Erik Jan Marinissen
European Test Symposium (ETS 2009), Sevilla, Spain, May 25-29, 2009 (Poster).
- Capture Power Reduction for Modular System-on-Chip Test
Jaynarayan T Tudu, Erik Larsson, Virendra Singh, Adit Singh
IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 8-10, 2009.
- On Minimization of Peak Power for Scan Circuit during Test
Jaynarayan T Tudu, Erik Larsson, Virendra Singh, Vishwani Agrawal
European Test Symposium (ETS 2009), Sevilla, Spain, May 25-29, 2009, pp. 25-30.
- Power-Aware System-Level DfT and Test Planning
Erik Larsson, C.P. Ravikumar
Book Chapter in "Power-Aware Testing and Test Strategies for Low Power Devices", Editors: Patrick Girard, Nicola Nicolici, Xiaoqing Wen, ISBN 978-1-4419-0927-5, Springer, 2009
- Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
Vinay N. S., Erik Larsson, Virendra Singh
DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 20-24, 2009.
- Fault-Tolerant Average Execution Time Optimization for System-On-Chips
Mikael Väyrynen, Virendra Singh, Erik Larsson
Frontiers of High Performance Embedded Computing, Bangalore, India, January, 2009.
- Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chips
Mikael Väyrynen, Virendra Singh, Erik Larsson
Design Automation and Test in Europe (DATE 2009), Nice, France, April 20-24, 2009, pp. 484-489.
- Test Response Compression for Diagnosis in Volume Production
Michael Söderman, Erik Larsson
DAC'08 Workshop on Diagnostic Services in Network-on-Chips (DSNOC), Anaheim, CA, USA, June 9, 2008.
- SOC Test Optimization with Compression-Technique Selection
Anders Larsson, Xin Zhang, Erik Larsson, Krishnendu Chakrabarty
A Workshop in Conjunction with the International Test Conference, Santa Clara, CA, USA, October 28-30, 2008 (Informal Digest).
- On Reduction of Capture Power for Modular System-on-Chip Test
Virendra Singh, Erik Larsson
IEEE Workshop on RTL and High Level Testing (WRTLT'08), Sapporo, JAPAN, November 27-28, 2008.
- Core-Level Expansion of Compressed Test Patterns
Anders Larsson, Xin Zhang, Erik Larsson, Krishnendu Chakrabarty
17th Asian Test Symposium (ATS), Sapporo, JAPAN, November 24-27, 2008, pp. 277-282.
- A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling
Erik Larsson, Zebo Peng
Journal of Electronic Testing: Theory and Application, Vol. 24, Issue 5, October 2008, pp. 497-504.
- An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
Erik Larsson
IET Computers and digital techniques, Vol. 2, Issue 4, July 2008, pp. 275-284(IET Computers & Digital Techniques Premium Award).
- Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 5, May 2008, pp. 973-977.
- Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Anders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Eles, Zebo Peng
Design, Automation, and Test in Europe (DATE 2008), Munich, Germany, March 10-14, 2008, 188- 193.
- An Integrated System-on-Chip Test Framework
Erik Larsson, Zebo Peng
Book Chapter in "The Most Influential Papers of 10 Years DATE", Editors: Rudy Lauwereins and Jan Madsen, ISBN 978-1-4020-6487-6, Springer, 2008
- Protocol Requirements in an SJTAG/IJTAG Environment
Erik Larsson, Gunnar Carlsson, Johan Holmqvist
Nordic Test Forum (NTF), November 2007, Snekkersten, Denmark.
- Protocol Requirements in an SJTAG/IJTAG Environment
Gunnar Carlsson, Johan Holmqvist, Erik Larsson
International Test Conference (ITC), Santa Clara, USA, October 21-26, 2007, Lecture 1.3 (pp. 1-9).
- What Impacts Course Evaluation?
Erik Larsson, Medhi Amirijoo, Daniel Karlsson, Petru Eles
12th SIGCSE Conf. on Innovation and Technology in Computer Science Education, Dundee, Scotland, UK, June 25-27, 2007, pp. 333-333.
- An Architecture for Combined Test Data Compression and Abort-on-Fail Test
Erik Larsson, Jon Persson
Asia and South Pacific Design Automation Conf. (ASP-DAC'07), Yokohama, Japan, January 23-26, 2007, pp. 726-731.
- Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
Tobias Dubois, Erik-Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters
Design, Automation, and Test in Europe (DATE), Nice, France, April 16-20, 2007, pp. 859-864.
- Test Data Truncation for Test Quality Maximisation under ATE Memory Depth Constraint
Erik Larsson, Stina Edbom
Journal on Computers & Digital Techniques, IET, Vol.1, Iss.1, January 2007, pp. 27-37.
- Improved Scan Chain Diagnosis
Erik-Jan Marinissen, Dan Adolfsson, Erik Larsson, Sandeep-Kumar Goel
15th NXP IC Test Symposium (NITS'07), Eindhoven, The Netherlands, June 11, 2007 (Informal Digest)
- Extended STAPL as SJTAG Engine
Johan Holmqvist, Gunnar Carlsson, Erik Larsson
IEEE European Test Symposium, Freiburg, Germany, May, 2007, pp. 119-124.
- A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07), Krakow, Poland, April 2007, pp. 61-66.
- Optimized Integration of Test Compression and Sharing for SOC Testing
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
Design, Automation, and Test in Europe Conference (DATE'07), Nice, France, April 2007, pp. 207-212.
- Combined Test Data Compression and Abort-on-Fail Test
Erik Larsson
24th Norchip Conference, Linkoping, Sweden, November 20-21, 2006
- High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO
Tobias Dubois, Mohamed Azimane, Erik Larsson, Erik-Jan Marinissen, Paul Wielage, Clemens Wouters
14th Philips Research IC Test Seminar (PRITS), Eindhoven, The Netherlands, June 27, 2006
- System-on-Chip Test Scheduling with Reconfigurable Core Wrappers
Erik Larsson, Hideo Fujiwara
IEEE Trans. on Very Large Scale Integration Systems (VLSI) Systems, Vol. 14, No. 3, March 2006, pp. 305-309
- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
Erik Larsson, Stina Edbom
Book Chapter in "Vlsi-Soc: From Systems To Silicon" (Editors: Ricardo Reis, Adam Osseiran, Hans-Joerg Pfleiderer), IFIP International Federation for Information Processing 240/2007, ISBN: 978-0-387-73660-0, Springer, 2007.
- Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng
International Test Conference (ITC'06), Santa Clara, California, USA, October 24-26, 2006, pp. 32.1 (1-10)
- SOC Test Scheduling with Test Set Sharing and Broadcasting
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
Swedish System-on-Chip Conference (SSoCC'06), Kolmården, Sweden, May 4-5, 2006 (Informal Digest)
- SOC Test Scheduling with Test Set Sharing and Broadcasting
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
IEEE Asian Test Symposium, Kolkata, India, December 18-21, 2005, pp. 162-167
- Introduction to Advanced System-on-Chip Test Design and Optimization
Erik Larsson
FRONTIERS IN ELECTRONIC TESTING: Vol.29, Springer, 2005, ISBN: 1-4020-3207-2
- Remote Boundary-Scan System Test Control for the ATCA Standard
David Bäckström, Gunnar Carlsson, Erik Larsson
International Test Conference (ITC'05), Austin, Texas, USA, November 8-10, 2005
- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
Erik Larsson, Stina Edbom
IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip (IFIP VLSI-SOC) 2005, Perth, Australia, October 17-19, 2005, pp. 429-434
- Multiple Constraints Driven System-on-Chip Test Time Optimization
Erik Larsson, Julien Pouget, Zebo Peng
Journal of Electronic Testing; Theory and Applications (JETTA), Volume 21, Number 6, December 2005, pp. 599-611
- Abort-on-Fail Based Test Scheduling
Erik Larsson, Julien Pouget, Zebo Peng
Journal of Electronic Testing; Theory and Applications (JETTA), Volume 21, Number 6, December 2005, pp. 651-658
- Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
Erik Larsson, Zebo Peng
Special Issue-Design and Test of Systems-On-a-Chip, IEEE Transactions on Computers, February 2006, Volume 6, Number 2, pp. 227-239
- A Test Data Compression Architecture with Abort-on Fail Capability
Erik Larsson, Irtiyaz Gilani
IEEE Workshop on RTL and High Level Testing (WRTLT), Harbin, China, July 20-21, 2005
- Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, 2005, pp. 403-409
- Boundary-Scan Test Control in the ATCA Standard
David Bäckström, Gunnar Carlsson, Erik Larsson
IEEE European Board Test Workshop, EBTW, Tallinn, Estonia, 25-26 May 2005
- Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
Urban Ingelsson, Sandeep-Kumar Goel, Erik Larsson, Erik-Jan Marinissen
IEEE European Test Symposium (ETS'05), Tallinn, Estonia, May 22-25, 2005, pp. 8-13
- A Constraint Logic Programming Approach to SOC Test Scheduling
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
Swedish System-on-Chip Conference (SSoCC'05), Tammsvik, Stockholm, Sweden, April 18-19, 2005 (Informal Digest)
- An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
Stina Edbom, Erik Larsson
2004 IEEE Asian Test Symposium (ATS 2004), Kenting, Taiwan, November 15-17, 2004, pp. 254-257
- Integrating Core Selection in the SOC Test Solution Design-Flow
Erik Larsson
International Test conference (ITC'04), Charlotte, NC, USA, October 2004, pp. 1349-1358
- Student-oriented Examination in a Computer Architecture Course
Erik Larsson, Anders Larsson
9th Annual Conference on Innovation and Technology in Computer Science Education, Leeds, UK, June 28-30, 2004, pp 245.
- A Technique for Optimization of System-on-Chip Test Data Transportation
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
9th IEEE European Test Symposium, Corsica, France, May 23-26, 2004, pp. 179-180. (Informal Digest)
- A Technique for Optimisation of SOC Test Data Transportation
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
Swedish System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004 (Informal Digest)
- Preemptive System-on-Chip Test Scheduling
Erik Larsson, Hideo Fujiwara
IEICE Transactions on Information Systems. Special Issue on Test and Verification of VLSI, Vol. E87-D, No. 3, March 2004, pp.620-629
- Core Selection Integrated in the SOC Test Solution Design-Flow
Erik Larsson
International Workshop on Test Resource Partitioning (TRP), Napa Valley, USA, April 2004
- Defect-Aware SOC Test Scheduling
Erik Larsson, Julien Pouget, Zebo Peng
2004 IEEE VLSI Test Symposium (VTS'04), Napa Valley, USA, April 2004, pp. 359-364
- Efficient Test Solutions for Core-based Designs
Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol.23, No.5, May 2004, pp. 758-775
- SOC Test Time Minimization Under Multiple Constraints
Julien Pouget, Erik Larsson, Zebo Peng
12th IEEE Asian Test Symposium (ATS03), Xian, China, November 17-19, 2003, pp. 312-317
- Optimal System-on-Chip Test Scheduling
Erik Larsson, Hideo Fujiwara
12th IEEE Asian Test Symposium (ATS03), Xian, China, November 17-19, 2003, pp. 306-311
- Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), Cambridge, MA, USA, November 3-5, 2003, pp. 385-392
- A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
Erik Larsson, Zebo Peng
International Test Conference (ITC) 2003, Charlotte, NC, USA, September 30 - October 2, 2003, pp. 1135-1144. (Paper 44.2)
- An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre
IEEE European Test Workshop 2003 (ETW'03), Maastricht, The Netherlands, May 25-28, 2003, pp 51-56 (Formal Proceedings)
- An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre
IEEE European Test Workshop 2003 (ETW'03), Maastricht, The Netherlands, May 25-28, 2003, pp. 117-122 (Informal Proceedings)
- Test Resource Partitioning and Optimization for SOC Designs
Erik Larsson, Hideo Fujiwara
2003 IEEE VLSI Test Symposium (VTS'03), Napa Valley, USA, 27 April - 1 May 2003, pp. 319-324
- Defect Probability-based System-On-Chip Test Scheduling
Erik Larsson, Julien Pouget, Zebo Peng
6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, Poland, April 14-16, 2003, pp. 25-32
- System-on-Chip Test Resource Partitioning and Optimization
Erik Larsson
Swedish System-on-Chip Conference (SSoCC'03), Sunbyholms Slott, Eskilstuna, Sweden, April 8-9, 2003 (Informal Digest)
- Optimal Test Time for System-on-Chip Designs using Preemptive Scheduling and Reconfigurable Wrappers
Erik Larsson, Hideo Fujiwara
Nara Institute of Science and Technology (NAIST), NAIST-IS-TR2002011, Japan, July 2002.
- Preemptive Power Constrained TAM Scheduling for Scan-based System-on-Chip
Erik Larsson, Hideo Fujiwara
Nara Institute of Science and Technology (NAIST), ISSN 0919-9527, NAIST-IS-TR2002003, Japan, January 2002.
- System-on-Chip Test Scheduling based on Defect Probability
Erik Larsson, Julien Pouget, Zebo Peng
2003 International Test Synthesis Workshop (ITSW), Santa Barbara, CA, USA, March 31 - April 2, 2003
- An Integrated Framework for the Design and Optimization of SOC Test Solutions
Erik Larsson, Zebo Peng
SOC (System-on-a-Chip) Testing for Plug and Play Test Automation.
Book Series: FRONTIERS IN ELECTRONIC TESTING, Volume 21, Krishnendu Chakrabarty (editor)
Kluwer Academic Publishers, ISBN 1-4020-7205-8, September 2002, pp. 21-36
- Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers
Erik Larsson, Hideo Fujiwara
Workshop on RTL and High Level Testing, Guam, USA, November 21-22, 2002
- Integrated Test Scheduling, Test Parallelization and TAM Design
Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
IEEE Asian Test Symposium (ATS'02), Tamuning, Guam, USA, November 18-20, 2002, pp. 397-404
- Power Constrained Preemptive TAM Scheduling
Erik Larsson, Hideo Fujiwara
European Test Workshop 2002, Corfu, Greece, May 26-29, 2002, pp. 119-126 (Formal Proceedings)
- Power Constrained Preemptive TAM Scheduling
Erik Larsson, Hideo Fujiwara
European Test Workshop 2002, Corfu, Greece, May 26-29, 2002, pp. 411-416 (Informal Digest)
- An Integrated Framework for the Design and Optimization of SOC Test Solutions
Erik Larsson, Zebo Peng
Journal of Electronic Testing; Theory and Applications (JETTA), for the Special Issue on Plug-and-Play Test Automation for System-on-a-Chip August 2002 issue (vol. 18, no. 4/5), pp. 385-400
- The Design and Optimization of SOC Test Solutions
Erik Larsson, Zebo Peng, Gunnar Carlsson
ICCAD-2001, DoubleTree Hotel, San Jose, California, November 4-8, 2001, pp. 523-530
- Test Scheduling and Scan-Chain Division Under Power Constraint
Erik Larsson, Zebo Peng
Tenth Asian Test Symposium (ATS 2001), Kyoto, Japan, November 19-21, 2001, pp. 259-264
- System-on-Chip Test Parallelization Under Power Constraints
Erik Larsson, Zebo Peng
European Test Workshop, Stockholm, Sweden, May 28-June 1, 2001.
- An Integrated System-On-Chip Test Framework
Erik Larsson, Zebo Peng
Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 13-16 March, 2001, pp. 138-144
- An Integrated System-Level Design for Testability Methodology
Erik Larsson
Ph. D. Thesis No. 660, Department of Computer and Information Science, Linköpings universitet, Sweden, December 2000.
- Test Infrastructure Design and Test Scheduling Optimization
Erik Larsson, Zebo Peng
European Test Workshop, Cascais, Portugal, May 23-26, 2000.
- A Technique for Test Infrastructure Design and Test Scheduling
Erik Larsson, Zebo Peng
Design and Diagnostic of Electronic Circuits and Systems Workshop (DDECS 2000), Smolenice Castle, Slovakia, April 5-7, 2000, pp. 26-29
- System-on-Chip Test Bus Design and Test Scheduling
Erik Larsson, Zebo Peng
International Test Synthesis Workshop, Santa Barbara, USA, March 6-8.
- An Estimation-based Technique for Test Scheduling
Erik Larsson, Zebo Peng
Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999, pages 25-28
- A Behavioral-Level Testability Enhancement Technique
Erik Larsson, Zebo Peng
IEEE European Test Workshop, Constance, Germany, May 25-28, 1999
- High-Level Testability Analysis and Enhancement Techniques
Erik Larsson
Licentiate Thesis No. 725, Linköpings Universitet, Linköping, Sweden, November 1998.
- Testability Analysis of Behavioral-Level VHDL Specifications
Erik Larsson, Zebo Peng
IEEE European Test Workshop , Barcelona, Spain, May 27-29, 1998.
- Early Prediction of Testability by Analyzing Behavioral VHDL Specifications
Erik Larsson, Zebo Peng
Norchip Conference, Tallinn, November 10-11, 1997. pp. 259-266
- A Controller Testability Analysis and Enhancement Technique
Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo Peng
European Design and Test Conference , Paris, March 17-20, 1997, pp. 153-157
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