Optimizing Fault Tolerance for Multi-Processor System-on-Chip
Book Chapter in "Design and Test Technology for Dependable Systems-on-chip", Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, ISBN: 978-1-6096-0212-3, 2010.
http://www.amazon.com/Design-Technology-Dependable-Systems-chip/dp/1609602129
ABSTRACT
[NVIL10] Dimitar Nikolov, Mikael Väyrynen, Urban Ingelsson, Erik Larsson, Virendra Singh, "Optimizing Fault Tolerance for Multi-Processor System-on-Chip", Book Chapter in "Design and Test Technology for Dependable Systems-on-chip", Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, ISBN: 978-1-6096-0212-3, 2010. |
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