Integrated Test Scheduling, Test Parallelization and TAM Design
IEEE Asian Test Symposium (ATS'02), Tamuning, Guam, USA, November 18-20, 2002, pp. 397-404
ABSTRACT
We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.
Remarks:
Best Paper Award at IEEE Asian Test Symposium 2002
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[LAFP02] Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng, "Integrated Test Scheduling, Test Parallelization and TAM Design", IEEE Asian Test Symposium (ATS'02), Tamuning, Guam, USA, November 18-20, 2002, pp. 397-404 |
