- Scan Cells Reordering to Minimize Peak Power During Test Cycle: A Graph Theoretic Approach
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.
- Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
Great Lakes Symposium on VLSI (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010, pp. 73-78.
- Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), Hongkong, China, November 27-28, 2009, pp. 43-48.
- System-on-Chip Test Scheduling with Reconfigurable Core Wrappers
Erik Larsson, Hideo Fujiwara
IEEE Trans. on Very Large Scale Integration Systems (VLSI) Systems, Vol. 14, No. 3, March 2006, pp. 305-309
- Preemptive System-on-Chip Test Scheduling
Erik Larsson, Hideo Fujiwara
IEICE Transactions on Information Systems. Special Issue on Test and Verification of VLSI, Vol. E87-D, No. 3, March 2004, pp.620-629
- Efficient Test Solutions for Core-based Designs
Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol.23, No.5, May 2004, pp. 758-775
- Optimal System-on-Chip Test Scheduling
Erik Larsson, Hideo Fujiwara
12th IEEE Asian Test Symposium (ATS03), Xian, China, November 17-19, 2003, pp. 306-311
- Test Resource Partitioning and Optimization for SOC Designs
Erik Larsson, Hideo Fujiwara
2003 IEEE VLSI Test Symposium (VTS'03), Napa Valley, USA, 27 April - 1 May 2003, pp. 319-324
- Optimal Test Time for System-on-Chip Designs using Preemptive Scheduling and Reconfigurable Wrappers
Erik Larsson, Hideo Fujiwara
Nara Institute of Science and Technology (NAIST), NAIST-IS-TR2002011, Japan, July 2002.
- Preemptive Power Constrained TAM Scheduling for Scan-based System-on-Chip
Erik Larsson, Hideo Fujiwara
Nara Institute of Science and Technology (NAIST), ISSN 0919-9527, NAIST-IS-TR2002003, Japan, January 2002.
- Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers
Erik Larsson, Hideo Fujiwara
Workshop on RTL and High Level Testing, Guam, USA, November 21-22, 2002
- Integrated Test Scheduling, Test Parallelization and TAM Design
Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
IEEE Asian Test Symposium (ATS'02), Tamuning, Guam, USA, November 18-20, 2002, pp. 397-404
- Power Constrained Preemptive TAM Scheduling
Erik Larsson, Hideo Fujiwara
European Test Workshop 2002, Corfu, Greece, May 26-29, 2002, pp. 119-126 (Formal Proceedings)
- Power Constrained Preemptive TAM Scheduling
Erik Larsson, Hideo Fujiwara
European Test Workshop 2002, Corfu, Greece, May 26-29, 2002, pp. 411-416 (Informal Digest)
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