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jaytu_glsvlsi10

Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power

Jaynarayan T. Tudu
 
Erik Larsson
Virendra Singh
 
Hideo Fujiwara

Great Lakes Symposium on VLSI (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010, pp. 73-78.

ABSTRACT
Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.


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[TLSF10] Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara, "Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power", Great Lakes Symposium on VLSI (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010, pp. 73-78.
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