System-on-Chip Test Parallelization Under Power Constraints
European Test Workshop, Stockholm, Sweden, May 28-June 1, 2001.
ABSTRACT
This paper deals with test parallelization (scan-chain sub-division) which is used as a technique to reduce test application time for systems-on-chip. An approach for test parallelization taking into account test conflicts and test power limitations is described. The main features of the proposed approach are the combination of test parallelization with test scheduling as well as the development of an extremely fast algorithm which can be used repeatedly in the design space exploration process. The efficiency and usefulness of our approach have been demonstrated with an industrial design.
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| ETW01.pdf | Adobe Acrobat portable document |
[LP01] Erik Larsson, Zebo Peng, "System-on-Chip Test Parallelization Under Power Constraints", European Test Workshop, Stockholm, Sweden, May 28-June 1, 2001. |
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