High-Level Testability Analysis and Enhancement Techniques
Licentiate Thesis No. 725, Linköpings Universitet, Linköping, Sweden, November 1998.
ABSTRACT
Hardware testing is an important issue in the development of digital systems and much research has been devoted to it. Most of this work deals with design for testability at low abstraction levels. In this thesis we deal with the test problems at the high abstraction levels. By considering the testability at an early design stage the test problems can be efficiently solved. We propose behavioral-level testability metrics based on an analysis of the variable range, operation testability and statement reachability. The metrics can be used to detect the hard-to-test parts with a low computational cost. By experiments we show the correlation between our metrics and the fault coverage when partial scan is used. We also show by experiments, where our technique is compared with a commercial gate-level tool, that it is possible to predict the testability on the behavioral-level accurately and efficiently. We have then developed a set of testability improvement transformations applicable direct on the behavioral VHDL specification with no restrictions on the high-level synthesis and a transformation selection strategy based on our testability metrics. We have also developed a controller testability analysis technique which is based on statement reachability and an enhancement technique consisting of branch control, loop termination and register initialization methods. The controller testability analysis and enhancement technique can be used for a register-transfer level design to improve its testability when the design is finally implemented, which is demonstrated by experiments with several benchmarks.
| Related files: |
|---|
| lic725el.ps.gz | postscript document, compressed (with gzip) |
[L98] Erik Larsson, "High-Level Testability Analysis and Enhancement Techniques", Licentiate Thesis No. 725, Linköpings Universitet, Linköping, Sweden, November 1998. |
|
