Power Constrained Test Scheduling for 3D Stacked Chips (poster)
1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA, November 4-5, 2010.
ABSTRACT
This paper addresses test application time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, lead to unnecessarily high TAT. This is because the final test of 3D SICs includes the testing of all the stacked chips. A key challenge in 3D SIC testing is to reduce TAT by cooptimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated BIST-engines and propose a test scheduling approach that reduces TAT while power constraints are met. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.
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[SIL10] Breeta SenGupta, Urban Ingelsson, Erik Larsson, "Power Constrained Test Scheduling for 3D Stacked Chips (poster)", 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA, November 4-5, 2010. |
