- Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
Breeta SenGupta, Urban Ingelsson, Erik Larsson
25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012.
- Test Planning for Core-based 3D Stacked ICs under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012.
- Test Planning for 3D Stacked ICs with Through-Silicon Vias
Breeta SenGupta, Urban Ingelsson, Erik Larsson
2nd IEEE Intl. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Anaheim, CA, USA, September 22-23, 2011.
- Scheduling Tests for 3D Stacked Chips under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
Journal of Electronic Testing: Theory and Applications (JETTA), Feb. 2012, Volume 28, Issue 1, pp. 121-135.
- Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster)
Breeta SenGupta, Urban Ingelsson, Erik Larsson
European Test Symposium (ETS 2011), Trondheim, Norway, May 23-27, 2011.
- Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Breeta SenGupta, Urban Ingelsson, Erik Larsson
The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
- Test Scheduling for 3D Stacked ICs under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011.
- Power Constrained Test Scheduling for 3D Stacked Chips (poster)
Breeta SenGupta, Urban Ingelsson, Erik Larsson
1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA, November 4-5, 2010.
- Scheduling Tests for 3D Stacked Chips Under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011.
- Scheduling Tests for Stacked 3D Chips under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
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