Multiplexed Redundant Execution: A Technique for Efficient Fault Tolerance in Chip Multiprocessors
Design Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010, pp. 1572-1577.
ABSTRACT
Continued CMOS scaling is expected to make future microprocessors susceptible to transient faults, hard faults, manufacturing defects and process variations causing fault tolerance to become important even for general purpose processors targeted at the commodity market.
To mitigate the effect of decreased reliability, a number of fault-tolerant architectures have been proposed that exploit the natural coarse-grained redundancy available in chip multiprocessors (CMPs). These architectures execute a single application using two threads, typically as one leading thread and one trailing thread. Errors are detected by comparing the outputs produced by these two threads. These architectures schedule a single application on two cores or two thread contexts of a CMP. As a result, besides the additional energy consumption and performance overhead that is required to provide fault tolerance, such schemes also impose a throughput loss. Consequently a CMP which is capable of executing 2n threads in non-redundant mode can only execute half as many (n) threads in fault-tolerant mode.
In this paper we propose multiplexed redundant execution (MRE), a low-overhead architectural technique that executes multiple trailing threads on a single processor core. MRE exploits the observation that it is possible to accelerate the execution of the trailing thread by providing execution assistance from the leading thread. Execution assistance combined with coarse-grained multithreading allows MRE to schedule multiple trailing threads concurrently on a single core with only a small performance penalty. Our results show that MRE increases the throughput of fault-tolerant CMP by 16% over an ideal dual modular redundant (DMR) architecture.
[SSKL10] Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson, "Multiplexed Redundant Execution: A Technique for Efficient Fault Tolerance in Chip Multiprocessors", Design Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010, pp. 1572-1577. |
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