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SaS Seminars 2011
Software and Systems Research Seminar Series
Autumn 2011
System Integration at ISY, LiU - background and status report (slides )
Dr. Ola Dahl , ISY, Linköpings universitet
Wednesday 30 nov 2011, 13:15, room Alan Turing
Abstract: System integration has been defined as new topic at ISY, aiming to bridge between existing disciplines such as computer engineering, communication systems, and automatic control. The work has been started, with Ola Dahl as associate professor since beginning of 2011. This talk will present system integration as of today, and two selected topics where ongoing work is done will be further described.
The first topic is Energy-Aware computing. In this work, we aim at finding models and methods for optimization of the trade-off between signal processing quality and processing cost, often expressed as requirements on power consumption. Initial work, relating the underlying hardware models and the energy consumed, will be presented. It can be seen that the energy required for a certain task varies very differently with respect to the number of operations when the hardware parameters change. This means that for certain tasks, a small change in the number of operations give a large saving in power consumption, while for other tasks this sensitivity is not so large.
The second topic is Requirements-driven modeling of 3GPP systems. It relates to system modeling in 3GPP systems, e.g. the currently developed systems for LTE and LTE-advanced. Our goal here is to use formal representations for selected 3GPP specifications, for the purpose of achieveing an increased system understanding, and also for making it possible to create tools, e.g. for code generation to simulators, and for code generation to products. Initial work, and ongoing discussions with Ericsson in Linköping, will be described in the talk.
Speaker's bio: Ola Dahl is Associate Professor in System integration, belonging to Computer Engineering division at ISY.
Before joining Linköping University, he worked at ST-Ericsson in Lund, Sweden, as senior staff engineer. He was mainly in charge of the development of virtual platforms to be able to simulate complicated hardware systems for software development in early phase. Meanwhile, he participated in system design work for advanced modem systems such as 3GPP LTE.
In his earlier career, he has been working both in industry and in university, mostly in the areas of software development, real-time systems, system simulation, and control system design. He has a PhD in Automatic Control from Lund University.
Software Engineering in the Multicore Era
Dr. Victor Pankratius , Karlsruhe Institute of Technology, Germany
Wednesday 23 nov 2011, 11:00 (!), room Alan Turing
Abstract: Multicore processors with several cores on the same chip are standard. Parallelism is now the key to better performance on every PC, laptop, or embedded device. The great challenge is now how to make parallel programming easier for average programmers. Motivated by results from empirical studies, this talk outlines solutions and new research directions in the areas of automatic performance tuning, language design, and debugging.
Speaker's bio: Dr. Pankratius heads the Multicore Software Engineering investigator group at the Karlsruhe Institute of Technology, Germany. He also serves as the elected chairman of the Software Engineering for parallel Systems (SEPARS) international working group. Dr. Pankratius' current research concentrates on how to make parallel programming easier. His work covers a range of research topics including auto-tuning, language design, debugging, software engineering in the cloud, and empirical studies. Contact him at http://www.victorpankratius.com.
Automated verification techniques for Infinite State Systems
Dr. Ahmed Rezine , ESLAB, IDA, Linköpings universitet
Tuesday 27 sep 2011, 13:15, room Alan Turing
Abstract: I will introduce myself and my work. My research looks at ways to extend automated verification techniques in general, and Model Checking in particular, to systems with unbounded state spaces. More concretely, I concentrate on augmenting the degree of automation in the verification of imperative sequential and concurrent programs. Model checking, especially after combination with symbolic techniques, is acknowledged as a breakthrough in the automatic verification of programs with a finite number of states. Nevertheless, programs commonly exhibit state spaces that can not be a priori bounded. Possible sources for this unboundedness are concurrency, unbounded data, dynamic data-structures and recursion. The verification problem for such common programs is undecidable in general and verification algorithms are necessarily incomplete. In this context, I concentrate in my work on augmenting the degree of automation when verifying programs with some of these sources, namely: concurrency, unbounded data, and dynamic data structures. I will give examples in the presentation of the kind of properties and systems I am looking at in my work: safety, parameterized systems, heap manipulating programs, or weak memory models.
Spring 2011
Optimal Code Generation for Explicitly Parallel Processors
Prof. Andreas Krall , TU Vienna, Austria
Date: Tuesday, 7 june 2011 Time: 10:15 Room: Alan Turing
Abstract:
In this talk ongoing work from a research project with the talk title is presented. The aim of this project is to develop techniques for optimal and heuristic integrated code generation for explicitly parallel processors (EPIC). First results on register reuse scheduling are presented where spilling of registers during register allocation is minimized by a local reordering of independent operations. On average 8.9% less values are spilled resulting in 3.4% reduction of static spill cost. Other ongoing work on scheduling for clustered architectures is discussed.
Speaker's biography:
Since February 1995 Andreas Krall is an associate professor for computer science (Praktische Informatik) at the Institut für Computersprachen, Technische Universität Wien. Since 2002 he is also managing the Christian Doppler research laboratory ``Compilation Techniques for Embedded Processors'' which is jointly funded by government and industry (Infineon, OnDemand Microelectronics). The main research interests of Andreas Krall are compilers and computer architecture. Current work are the development of an architecture description language with automatic generation of optimizing compilers, high performance instruction set simulators and VHDL processor descriptions. Other important topics are all kind of optimizations (instruction selection, register allocation, instruction scheduling, program analysis), static and dynamic binary translation and the Java virtual machine CACAO (www.cacaovm.org). Andreas Krall (co)authored more than 80 journal and conference articles and is a member in the ARTIST2 and HiPEAC European networks of excellence.
An End-to-End Solution for Product Quality and Reliability
Dr. Xinli Gu, Huawei Technologies, USA
Date: Friday May 20. Time: 13:15 Room: John von Neumann
Abstract:
System quality and reliability requires a complete End-to-End solution, from component design or purchase, to board and software design, board and system manufacturing, and system in-field health monitoring. Many built-in self monitors, self tests, self adjustment and self repair technologies are designed in the system. Adaptive concept is also a key to achieve the effect of the End-to-End solution. This presentation covers a best practice in industry deploying these concepts into real products with most advanced DFX technologies.
Speaker's Bio: Xinli Gu is a Senior Director with Huawei Technologies, USA, leading design solution and driving corporate process for product quality and reliability. Before joining Huawei, he is a director with Cisco Systems, Inc. for more than 12 years, responsible for corporate level product quality, Time-to-Market, manufacturing test/diagnosis cost reduction, and product yield improvement. Xinli also worked for Synopsys in California and Ericsson in Sweden. He received a BSc in Computer Science from Shanghai JiaoTong University, and MSc and PhD in Computer Engineering from Linkoping University, Sweden. He has published over 30 technical papers and holds several US patents.
Evaluating Design Trade-offs in Customizable Processors
Dr. Unmesh Bordoloi , ESLAB, IDA, Linköping university, Sweden
Date: Wednesday April 27, 2011. Place: Alan Turing Time: 10:15
Abstract:
The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly focused on single criteria optimization, e.g., optimizing performance though custom instructions under pre-defined area constraint. From the designer's perspective, however, it would be more interesting if the conflicting trade-offs among multiple objectives (e.g., performance versus area) are exposed enabling an informed decision making. In this talk, we will present two frameworks, for uniprocessor and Multiprocessor System-on-Chips (MPSoC), that systematically evaluate the design performance-area trade-offs. In the context of uniprocessors, we will discuss multi-tasking real-time embedded applications while for the MPSoC setting, we will focus on multimedia streaming applications. Our proposed frameworks can efficiently and accurately evaluate the different customization choices without resorting to expensive system-level simulations.
Speaker's Bio: Unmesh Bordoloi is a post‐doctoral researcher at Embedded Systems Lab, Linköping University. Prior to joining LiU, he spent one year as a post‐doctoral researcher at the Verimag Laboratory in Grenoble, France. He obtained his PhD from the School of Computing at the National University of Singapore in 2008. He was awarded the President's Graduate Fellowship and the Sun Microsystems Ph.D. Fellowship' for his research work at the National University of Singapore; HiPEAC Paper Award in 2009 and the Best Paper Award at 8th International Conference on Embedded and Ubiquitous Computing, 2010. His research focuses on system-level design and analysis issues like schedulability analysis, hardware/software co-design, and fault tolerance.
Self-organizing Telecom Networks
Stefan Engström, Ericsson AB
Date: Tuesday Apr 19, 2011. Place: Alan Turing Time: 15:15
Abstract:
With the introduction of 4G in the telecom networks, the interest in self-organizing networks has suddenly awoken.
The seminar briefly discusses the evolution of the mobile networks and why the operators suddenly have become interested in automatically controlling their networks. If also describes some functions to rationalize the build out and optimize the performance of the radio network.
Transactional Memory
Prof. Pascal Felber , University of Neuchatel, Switzerland
Date: Thursday Jan 13, 2011. Place: Alan Turing Time: 13:00 (!)
Abstract:
Major chip manufacturers are stirring what is perceived by many specialists as a revolution in modern computing, by changing their focus from ever higher processor speed to increased parallel processing capabilities. With multi-core and multi-processor systems becoming commonplace, applications must rely on multi-threading for performance and the lack of effective abstractions to manage the complexity of concurrent programming represents a major hurdle for software developers. Software transactional memory (STM) is a recent programming model in which concurrent threads synchronize optimistically via lightweight transactions rather than pessimistically using locks. STM has better real-time properties than lock-based synchronization primitives (e.g., there is no priority inversion problem), improves scalability for certain data access patterns, and is composable. STM provides atomicity properties that can also be used to develop robust applications. This talk will present the basic principles underlying STM, as well as recent research in building efficient STMs.
After the SaS seminar, there will also be another presentation (from 14:00, same room, as RTSLAB seminar) by the same speaker:
SPLAY: Distributed Systems Evaluation Made Simple
Date: Thursday Jan 13, 2011. Place: Alan Turing Time: 14:00
Abstract:
This talk will present SPLAY, an integrated system that facilitates the design, deployment and testing of large-scale distributed applications. Unlike existing systems, SPLAY covers all aspects of the development and evaluation chain. It allows developers to express algorithms in a concise, simple language that highly resembles pseudo-code found in research papers. The execution environment has low overheads and footprint, and provides a comprehensive set of libraries for common distributed systems operations. SPLAY is freely available from http://www.splay-project.org/.
Speaker's bio:
Pascal Felber received his M.Sc. and Ph.D. degrees in Computer Science from the Swiss Federal Institute of Technology. From 1998 to 2002, he has worked at Oracle Corporation and Bell-Labs (Lucent Technologies) in the USA. From 2002 to 2004, he has been an Assistant Professor at Institut EURECOM in France. Since October 2004, he is a Professor of Computer Science at the University of Neuchâtel, Switzerland, working in the field of dependable and distributed systems. He has published over 80 research papers in various journals and conferences.
Testing Web Applications with the Atomic Section Model
Prof. Jeff Offutt , George Mason University
Date: Tuesday Jan 11, 2011. Place: Alan Turing Time: 13:15
Abstract:
Web software applications are complex, sophisticated programs that use novel computing technologies. The widespread use of the Web to deploy software means faults can have far reaching consequences. This is particularly important given the current use of web software to control critical infrastructure. Although web applications share some characteristics with client-server, distributed, and traditional programs, they also introduce novel features. Web software introduces new types of execution flow, new levels of variable scoping, the ability for users to directly change the potential flow of execution, dynamic creation of parts of the user interface, and distributed integration. These allow the potential control flow to vary with each execution, preventing the possible control flows from being determined.
This talk will present a novel modeling technique for web software that describes possible user interactions. The talk will present results from using this model to design tests and suggest other uses of the model, including maintenance and design.
Speaker's Biography
Dr. Jeff Offutt is Professor of Software Engineering at George Mason University. He has invented numerous test strategies, published over 130 refereed research papers, and is co-author of the textbook Introduction to Software Testing. He is editor-in-chief of Wiley's journal of Software Testing, Verification and Reliability; steering committee chair for the IEEE International Conference on Software Testing, Verification, and Validation; and was program chair for ICST 2009. He has consulted with numerous companies on software testing, usability, and software intellectual property issues. Offutt is on the web at http://www.cs.gmu.edu/~offutt/.
Page responsible: Christoph Kessler
Last updated: 2012-08-17
