Professor for Computer Science at Linköping University, Sweden

Christoph Kessler

Prof. Dr. Christoph Kessler
PELAB - Programming Environments Laboratory
Software and Systems Division
Department for Computer and Information Science (IDA)
Linköping University
S - 581 83 Linköping, Sweden

Office: PELAB, B-house, room 3B:474
phone +46 13 28 2406
mobil +46 70 3666687
email: Christoph.Kessler \at liu.se
URKUND-address: chrke55.liu \at analys.urkund.se

Research

Teaching, Thesis projects

Administration

Research

Parallel computing
- Parallel programming models, languages, compilers, run-time systems, tools, libraries, algorithms
  - especially for heterogeneous multicore / manycore platforms such as Cell, GPU-based systems, NoC
- Automated synthesis of parallel programs from parallel building blocks
- Resource allocation, mapping, frequency scaling, and scheduling of parallel computations to parallel systems
- Modeling of hardware and software properties for energy and performance optimizations
- Performance portability
Compiler technology
- Code generation for instruction-level parallel and embedded processors
- Optimization problems in code generation
- Retargetability
- Program analysis and transformation, including automatic and semiautomatic parallelization

List of publications

Short CV

PhD students

Recent / upcoming events:

Euro-Par 2018 conference, Topic 9: Multicore and Manycore Methods and Tools

Current or recently completed projects and activities:

EU H2020 FETHPC project Enhancing Programmability and boosting Performance Portability for Exascale Computing Systems (EXA2PRO)
May 2018-Apr. 2021

SkePU: Auto-tunable skeleton programming framework for Multicore CPU and multi-GPU systems
A framework for high-level, structured, portable parallel programming of heterogeneous systems.
Open-source software project since 2010. Current version: SkePU 2.0.

EU FP7 project Execution Models for Energy-Efficient Computing Systems (EXCESS)
Sep. 2013-Aug. 2016.
- Language and tool infrastructure for energy-aware application synthesis, system modeling, performance and energy modeling, optimization techniques and autotuning for holistic energy optimization for heterogeneous multicore systems
- Partly based on our previous work for FP7 project PEPPHER
- Leading Workpackage 1 (Execution, Platform and Programming Models for Energy Optimization)
- SkePU: auto-tunable skeleton programming library for Multicore CPU and Multi-GPU systems
- MeterPU: generic, portable measurement abstraction library for Multicore CPU and Multi-GPU systems
- Global Composition Framework
- XPDL extensible platform description language
- Automated performance modeling for guiding automatic selection in multi-variant computations
- Short overview of our contributions to EXCESS (Proc. EXCESS workshop Gothenburg, Sweden, Aug. 2016)

EU ICT COST Action IC1406 High-Performance Modelling and Simulation for Big Data Applications (cHiPSet)
2015-2019
Vice leader of Working Group 2 (Parallel Programming Models)

Mapping and Scheduling Moldable-Parallel Streaming Tasks on Many-Core Processors
We consider the combined problem of allocating cores, mapping, and discrete voltage/frequency scaling for moldable (i.e., parallelizable) streaming tasks to manycore processors, in order to optimize energy usage given a throughput constraint.
This is partly based on our earlier work on on-chip-pipelining.
- Crown Scheduling, Proc. PATMOS-2013 conference, IEEE, DOI: 10.1109/PATMOS.2013.6662176
- Fast Crown Scheduling Heuristics for Energy-Efficient Mapping and Scaling of Moldable Streaming Tasks on Many-Core Systems,
  ACM Trans. on Arch. and Code Opt. 11(4), Jan. 2015, DOI: 10.1145/2687653
- Drake generic framework for generating on-chip pipelined code from streaming task graphs for many-core systems

SeRC-OpCoReS: Optimized Composition and Runtime Support for e-Science
Partially funded by the Swedish e-Science Research Center (SeRC), SeRC core section on Parallel and Distributed Algorithms and Tools (2011-2015) and Parallel Software and Data Engineering (2016-2018).

Frameworks for high-level parallel programming of heterogeneous multicore systems
with skeletons, patterns and containers:
- SkePU: Auto-tunable skeleton programming library for GPU-based systems.
- BlockLib: Skeleton programming library for Cell/B.E.
- PRT Pattern Recognition Tool: Generic tool for automated recognition of computational patterns in legacy C programs, e.g. for pattern-based automatic parallelization.

HPC-Europa3 (H2020, 2017-2021) scientific host

PELAB research group on compiler technology and parallel computing

Former Projects:

Performance Portability and Programmability for Heterogeneous Many-core Architectures (PEPPHER)
EU FP7 project, Jan. 2010 - Dec. 2012.
- Leading Workpackage 1 (Compositional parallel software development)
- SkePU - Auto-tunable, Multi-Backend Skeleton Programming Framework for Multicore and Multi-GPU Systems
- The PEPPHER Composition Tool
- Survey article in IEEE Micro, 2011
- PEPPHER i LIU-Forskningsnyheterna (Apr 2010)
Integrated Code Generation for Instruction-Level Parallel Architectures
- OPTIMIST: Optimization algorithms for integrated code generation
  OPTIMIST is a retargetable, highly optimizing code generator for superscalar, VLIW, clustered VLIW, DSP and embedded processor architectures.
  To achieve high code quality, it simultaneously considers the optimization problems for instruction selection (including cluster assignment and resource allocation), instruction scheduling, and register allocation.
  Partially funded 2001-2007 by CENIIT and 2004-2005 by SSF RISE.
- Integrated Software Pipelining
  Optimal code generation for loops, integrating both instruction selection, cluster assignment, scheduling and register allocation including optimal spill code generation and scheduling, for embedded, VLIW and clustered VLIW processors.
  Funded 2006-2008 and 2010-2012 by Vetenskapsrådet (VR) and 2006-2011 by the CUGS graduate school.

REPLICA project (contract research).
This VTT project developed a reconfigurable shared memory chip multiprocessor supporting strong memory consistency (CRCW PRAM on a chip). We developed a high-level parallel programming language, a compiler backend and system support for the REPLICA architecture.

DSP Platform for Emerging Telecommunication and Multimedia (ePUMA)
Optimizing DSP streaming applications for memory access cost on a new reconfigurable chip multiprocessor.
WP3: Classification of memory access patterns in DSP applications; program analysis for memory access structures, and automatic selection of most suitable network configuration for parallel memory access.
Funded 2008-2011 by SSF
- PRT Pattern Recognition Tool
  Generic tool for automated recognition of computational patterns in legacy C programs, e.g. for pattern-based automatic parallelization.

On-chip pipelining of memory-intensive computations on multi-/manycore processors (Cell/B.E. and Intel SCC)
Restructuring memory-intensive, streamable computations such as parallel mergesort to use on-chip forwarding of intermediate data between Cell SPEs allows to reduce the overall volume of off-chip memory accesses, making the application less memory bound and resulting in faster computation. We develop mapping algorithms that optimize trade-offs between computational load balance, on-chip buffer requirements and on-chip communication volume in on-chip pipelining.
Applied to mergesort on Cell, this speeds up the dominating global merge phase of CellSort by up to 70% on QS-20 and up to 143% on PlayStation-3, see our paper at Euro-Par 2010.

Fork: Fork95 Language Definition and Compiler for the SB-PRAM, a scalable, massively parallel shared memory MIMD computer with uniform memory access time that works synchronously at the instruction level. The complete project is described in my recent book. The compiler and tools developed for the SB-PRAM are now used in programming labs for teaching parallel algorithms.
SPARAMAT A tool for automatic detection of sparse matrix computations and data structures in application programs by static and dynamic pattern matching techniques, which can be used for automatic parallelization and aggressive program transformations. (The successor of the former PARAMAT project at Saarbrücken.) Funded 1997-2000 by Deutsche Forschungsgemeinschaft (DFG)
NestStep
Design and implementation of a MIMD parallel global address space (PGAS) language based on the BSP (bulk-synchronous parallel) programming model, supporting shared variables and nested parallelism on top of message passing architectures.
NestStep provides deadlock-free, deterministic parallel execution with BSP-compliant synchronicity and memory consistency.
NestStep has been implemented for MPI clusters and for the heterogeneous multicore processor Cell/B.E.
Interactive Invasive Parallelization
User-guided composition of parallel software with an incremental aspect-oriented parallelization approach.
Covers both automatic parallelization, skeleton-based structured parallel programming and semiautomatic program restructuring.
Support for automatic roundtrip engineering in aspect weaving.
Part of the RISE project funded 2002-2005 and 2006-2007 by SSF.