Lab Assignment 1: Cache Memories

Table of Contents

• Objective
• Time allocation
• Theoretical background
• Assignments
• What to report
• Resources

Objective

The purpose of this lab is to understand the functionality of cache memories, and to get an insight into various trade-offs related to the design of systems with cache memories.

Time allocation

4 hours (2 lab sessions) are allocated for this lab.

Theoretical background

You should review the folowing resources before you start working on this lab:

• Notes from the 2nd course lecture
• Chapter 4 (on cache memories) in the course book
• Lab 0: Using SimpleScalar at IDA's Machines

Assignments

1. Cache basics
   Solve problem 4.8 in 9th edition of the course book. (Note: the size of the memory should be 2^8 bytes instead of 28 bytes.) It is a similar problem as 4.8 in the 7th and 8th edition of the book. You can also find the text of the problem from this URL.


2. Locality of data
   This assignment requires you to use sim-cache for the simulations on two different architectures.
   You need to run two test programs on each of the two architectures.
   The source code and the binaries of the test programs are of the .c and .ss suffix, respectively.
   The configuration files for simulations are of the .cfg suffix.
   You can get the test programs and the configuration files for simulations by copying the files from the following directory.
   
   cp -r ~/TDTS08 TDTS08
   To complete this assignment, please follow the instructions listed below.
   • Run simulations of both test programs (test1.ss and test2.ss) with both configuration files (cache1.cfg and cache2.cfg).
     
   • Look into the configuration files, cache1.cfg and cache2.cfg, used for the simulations.
     Compare the architectures on which the test programs were run.
   • Analyze the C source code of both test programs, namely test1.c and test2.c.
     Understand how the data are accessed.
     Identify the spatial and temporal locality of the data from the source code.
     Are the two test programs functionally equivalent?
   • Extract the miss rates from the output files of the simulations.
     Explain the differences in hit/miss rates in each case.
     Based on these results, think of a relation between the cache associativity and the locality of data.


3. Evaluation of cache configurations
   

   This assignment requires you to use sim-cheetah in order to evaluate the performance of several cache configurations.

   • Create a configuration file for sim-cheetah, so that the simulations cover the following cache configurations:
     • caches with a number of sets between 128 and 4096,
     • caches with a level of associativity between 1 and 8,
     • caches with a line size of 32 bytes and a LRU replacement policy.
     ATTENTION: For those arguments that are commented with "log base 2", you should use the value of power instead of the original value. For example, if you want to set the line size of the cache to be 64, you should set 6 instead of 64 in the line with a leading switch -l.

     Using the go.ss benchmark available under bin folder, run the simulation for the three cases in which the cache stores either only data (data cache), or only intructions (instruction cache), or both (unified cache).

     Here is an example of runnning go.ss on SimpleScalar:

     sim-cheetah -config config-file ~/TDTS08/bin/go.ss 3 7
     where go.ss is a simple program that makes the computer run the game "Go" against itself.
     The first parameter (3) indicates the level of the player, while the second parameter (7) sets the go table size.

   • For each of the three simulations, extract the results from the output files, and create a plot graph which shows how the miss ratio depends on the associativity. You can use OpenOffice or any other tools to plot the data.
   • Answer the following questions.
   • What is the relation between the miss ratio and: the associativity, number of sets, cache size?
   • Compare the overall performance of the data, instruction, and unified caches.
   • In your opinion, why are such cache evaluations necessary for a designer?
     Give a numeric example based on the results obtained from the simulation.

What to report

• Answers (with sufficient explanations) to each of the previous problems. You may use figures when necessary.

Resources

• The help file on running the examples.
• Lecture notes on cache memories.
• D. Burger, and T. M. Austin, The SimpleScalar Tool Set, Version 2.0, 1997.
• T. M. Austin, A User's and Hacker's Guide to SimpleScalar Architectural Tool Set, 1997.
• William Stallings, Computer Organization and Architecture, 9th edition.

Page responsible: Zebo Peng
Last updated: 2015-11-06