TDTS08 Advanced Computer Architecture (2026) (6 ECTS)
HT1 2026
Welcome to the homepage of the Advanced Computer Architecture course TDTS08.
Latest News...
| 25 September | Update to Lab 1 |
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The instructions for the third question in Assignment 2 have been revised to improve clarity and readability, as follows. Consider the nested loops in both test programs (Lines 22-26 in
For each combination, calculate the cache miss ratio for the accesses to array
To help with the calculation, think about the access pattern to array
Assume that the cache is empty when the nested loop starts and that an Finally, identify which of the four combinations gives the lowest miss ratio and which gives the highest miss ratio. |
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| 25 September | Update to Lab 3 |
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The following note has been added to Lab 3 (If you have already completed Lab 3, there is no need to redo the experiment. This update does not substantially affect the experimental results or conclusions and is mainly intended to provide additional clarification.): |
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| 25 September | Lab 5 Submission |
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Please submit the report for Lab 5 via Lisam. Only one report is required per group. |
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Last updated: 2025-08-20
