- Hybrid BIST Energy Minimisation Technique for System-on-Chip Testing
Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng
IEE Proceedings - Computers and Digital Techniques, Vol. 153 , Issue 4, July 2006, pp. 208-216
- Hybrid BIST Methodology for Testing Core-Based Systems
Gert Jervan, Raimund Ubar, Zebo Peng
Proceedings of the Estonian Academy of Sciences. Engineering, Vol. 12, No. 3-2, September 2006, pp. 300–322
- Test Time Minimization for Hybrid BIST of Core-Based Systems
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
Journal of Computer Science and Technology, Vol. 21, No. 6, November 2006, pp. 907-912
- Off-line Testing of Delay Faults in NoC Interconnects
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng
9th Euromicro Conference on Digital System Design (DSD 2006), Cavtat near Dubrovnik, Croatia, August 30 - September 1, 2006, pp. 677-680
- Test Generation: A Hierarchical Approach
Gert Jervan, Raimund Ubar, Zebo Peng, Petru Eles
Chapter in System-level Test and Validation of Hardware/Software Systems, Springer Series in Advanced Microelectronics, Vol. 17, ISBN 1-85233-899-7, 2005
- An Approach to System-Level DFT
Gert Jervan, Raimund Ubar, Zebo Peng, Petru Eles
Chapter in System-level Test and Validation of Hardware/Software Systems, Springer Series in Advanced Microelectronics, Vol. 17, ISBN 1-85233-899-7, 2005
- Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment
Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng
10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005, pp. 2-7
- An Improved Estimation Technique for Hybrid BIST Test Set Generation
Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina
IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp. 182-185
- An Improved Estimation Methodology for Hybrid BIST Cost Calculation
Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina
IEEE Norchip 2004, Oslo, Norway, November 8-9, 2004, pp. 297-300
- An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
Swedish System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004 (Informal Digest)
- An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
The 5th IEEE Latin-American Test Workshop, Cartagena, Colombia, March 8-10, 2004, pp. 98-103
- Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
The IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), Perth, Australia, January 28-30, 2004, pp. 3-8
- Test Time Minimization for Hybrid BIST of Core-Based Systems
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
12th IEEE Asian Test Symposium (ATS03), Xian, China, November 17-19, 2003, pp. 318-323
- Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
The 21st NORCHIP Conference, Riga, Latvia, November 10-11, 2003, pp. 112-116
- Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), Cambridge, MA, USA, November 3-5, 2003, pp. 225-232
- Integrated Design and Test Generation Under Internet Based Environment MOSCITO
Andre Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatova, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng
EUROMICRO Symposium on Digital System Design (DSD'2002), Dortmund, Germany, Sept. 4-6, 2002, pp. 187-194
- High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory
Andre Schneider, Karl-Heinz Diener, Gert Jervan, Zebo Peng, Jaan Raik, Raimund Ubar, Thomas Hollstein, Manfred Glesner
The 8th biennial Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002, pp. 287-290
- A Hybrid BIST Architecture and its Optimization for SoC Testing
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
IEEE 2002 3rd International Symposium on Quality Electronic Design (ISQED'02), March 18-20, 2002, San Jose, California, USA, pp. 273-279
- Using Tabu Search Method for Optimizing the Cost of Hybrid BIST
Raimund Ubar, Helena Kruus, Gert Jervan, Zebo Peng
16th Conference on Design of Circuits and Integrated Systems (DCIS 2001), Porto, Portugal, November 20-23, 2001, pp. 445-450
- Fast Test Cost Calculation for Hybrid BIST in Digital Systems
Raimund Ubar, Gert Jervan, Zebo Peng, Elmet Orasson, Rein Raidma
Euromicro Symposium on Digital Systems Design, Warsaw, Poland, Sept. 4-6, 2001, pp. 318-325
- Challenges for Future System-on-Chip Design
Thomas Hollstein, Zebo Peng, Raimund Ubar, Manfred Glesner
15th European Conference on Circuit Theory and Design, Espoo, Finland, August 28-31, 2001
- Improving the Efficiency of Timing Simulation of Digital Circuits
Artur Jutman, Raimund Ubar, Zebo Peng
Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, 13-16 March, 2001, pp. 460-466
- Test Cost Minimization for Hybrid BIST
Gert Jervan, Zebo Peng, Raimund Ubar
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'2000), Yamanashi, Japan, 25-27 October, 2000, pp. 283-291.
- High-level Test Synthesis with Hierarchical Test Generation
Gert Jervan, Petru Eles, Zebo Peng, Jaan Raik, Raimund Ubar
IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 1999, pages 291-296
- Hierarchical Test Generation for Digital Systems
Marina Brik, Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar
Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp. 131-136, 1998.
- Hierarchical Test Generation with Multi-Level Decision Diagram Models
Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar
7th IEEE North Atlantic Test Workshop, West Greenwich, RI, USA, pp. 26-33, May 28-29, 1998.
- DECIDER: A Decision Diagram based Hierarchical Test Generation System
Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar
DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998.
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