An Improved Estimation Technique for Hybrid BIST Test Set Generation
IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp. 182-185
ABSTRACT
This paper presents an improved estimation technique for hybrid BIST test set generation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is determined by the ratio of those test patterns in the final test set. Unfortunately, exact algorithms for finding the optimal test sets are computationally very expensive. And several heuristics have been developed to address this problem based on estimation methods. In this paper we propose an improved estimation technique for fast generation of the hybrid test set. The technique is based on fault simulation results, and experiments have shown that the proposed technique is more accurate than the estimation methods proposed earlier.
| Related files: |
|---|
| ddecs05.pdf | Adobe Acrobat portable document |
Copyright note for papers published by the IEEE Computer Society:
Copyright IEEE. Personal use of this material is permitted. However,
permission to reprint/republish this material for advertising or
promotional purposes or for creating new collective works for resale
or redistribution to servers or lists, or to reuse any copyrighted
component of this work in other works, must be obtained from the IEEE.
[JPUK05] Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina, "An Improved Estimation Technique for Hybrid BIST Test Set Generation", IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp. 182-185 |
