Off-line Testing of Delay Faults in NoC Interconnects
9th Euromicro Conference on Digital System Design (DSD 2006), Cavtat near Dubrovnik, Croatia, August 30 - September 1, 2006, pp. 677-680
ABSTRACT
Testing of high density SoCs operating at high clock speeds in an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for on-line testing.
[BJKU06] Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng, "Off-line Testing of Delay Faults in NoC Interconnects", 9th Euromicro Conference on Digital System Design (DSD 2006), Cavtat near Dubrovnik, Croatia, August 30 - September 1, 2006, pp. 677-680 |
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