Project's Title
Project Description
- Hybrid BIST Energy Minimisation Technique for System-on-Chip Testing
Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng
IEE Proceedings - Computers and Digital Techniques, Vol. 153 , Issue 4, July 2006, pp. 208-216 - Hybrid BIST Methodology for Testing Core-Based Systems
Gert Jervan, Raimund Ubar, Zebo Peng
Proceedings of the Estonian Academy of Sciences. Engineering, Vol. 12, No. 3-2, September 2006, pp. 300–322 - Test Time Minimization for Hybrid BIST of Core-Based Systems
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
Journal of Computer Science and Technology, Vol. 21, No. 6, November 2006, pp. 907-912 - Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems
Gert Jervan
Ph. D. Thesis No. 945, Dept. of Computer and Information Science, Linköping University, May 2005 (Opponent: Prof. Joao Paulo Teixeira, IST/INSESC-ID, Portugal) - Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
Zhiyuan He, Gert Jervan, Petru Eles, Zebo Peng
8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, 2005, pp. 83-86 - Test Generation: A Hierarchical Approach
Gert Jervan, Raimund Ubar, Zebo Peng, Petru Eles
Chapter in System-level Test and Validation of Hardware/Software Systems, Springer Series in Advanced Microelectronics, Vol. 17, ISBN 1-85233-899-7, 2005 - An Approach to System-Level DFT
Gert Jervan, Raimund Ubar, Zebo Peng, Petru Eles
Chapter in System-level Test and Validation of Hardware/Software Systems, Springer Series in Advanced Microelectronics, Vol. 17, ISBN 1-85233-899-7, 2005 - Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment
Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng
10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005, pp. 2-7 - An Improved Estimation Technique for Hybrid BIST Test Set Generation
Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina
IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp. 182-185 - Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
Swedish System-on-Chip Conference (SSoCC'05), Tammsvik, Stockholm, Sweden, April 18-19, 2005 (Informal Digest) - Hybrid BIST Test Scheduling Based on Defect Probabilities
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
2004 IEEE Asian Test Symposium (ATS 2004), Kenting, Taiwan, November 15-17, 2004, pp. 230-235 - An Improved Estimation Methodology for Hybrid BIST Cost Calculation
Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina
IEEE Norchip 2004, Oslo, Norway, November 8-9, 2004, pp. 297-300 - An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
Swedish System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004 (Informal Digest) - An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
The 5th IEEE Latin-American Test Workshop, Cartagena, Colombia, March 8-10, 2004, pp. 98-103 - Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
The IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), Perth, Australia, January 28-30, 2004, pp. 3-8 - Test Time Minimization for Hybrid BIST of Core-Based Systems
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
12th IEEE Asian Test Symposium (ATS03), Xian, China, November 17-19, 2003, pp. 318-323 - Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
The 21st NORCHIP Conference, Riga, Latvia, November 10-11, 2003, pp. 112-116 - Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), Cambridge, MA, USA, November 3-5, 2003, pp. 225-232 - High-Level and Hierarchical Test Sequence Generation
Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante
Swedish System-on-Chip Conference (SSoCC'03), Sunbyholms Slott, Eskilstuna, Sweden, April 8-9, 2003 (Informal Digest) - High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems
Gert Jervan
Licentiate Thesis No. 973, Dept. of Computer and Information Science, Linköping University, Oct. 2002 - High-Level and Hierarchical Test Sequence Generation
Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante
IEEE International Workshop on High Level Design Validation and Test, Cannes, France, October 27-29, 2002, pp. 169-174 - High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory
Andre Schneider, Karl-Heinz Diener, Gert Jervan, Zebo Peng, Jaan Raik, Raimund Ubar, Thomas Hollstein, Manfred Glesner
The 8th biennial Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002, pp. 287-290 - Report D1: Report on benchmark identification and planning of experiments to be performed
Gert Jervan, Zebo Peng, Matteo Sonza Reorda, Massimo Violante
COTEST Project Report, Politecnico di Torino, Linköping University, 2002. - Report D4: Final Report on Project Results
Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante, Petru Eles, Gert Jervan, Zebo Peng
COTEST Project Report, Politecnico di Torino, Linköping University, 2002. - Report D5: Report on Dissemination Plan
Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante, Petru Eles, Gert Jervan, Zebo Peng
COTEST Project Report, Politecnico di Torino, Linköping University, 2002. - A Hybrid BIST Architecture and its Optimization for SoC Testing
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
IEEE 2002 3rd International Symposium on Quality Electronic Design (ISQED'02), March 18-20, 2002, San Jose, California, USA, pp. 273-279 - Using Tabu Search Method for Optimizing the Cost of Hybrid BIST
Raimund Ubar, Helena Kruus, Gert Jervan, Zebo Peng
16th Conference on Design of Circuits and Integrated Systems (DCIS 2001), Porto, Portugal, November 20-23, 2001, pp. 445-450 - Fast Test Cost Calculation for Hybrid BIST in Digital Systems
Raimund Ubar, Gert Jervan, Zebo Peng, Elmet Orasson, Rein Raidma
Euromicro Symposium on Digital Systems Design, Warsaw, Poland, Sept. 4-6, 2001, pp. 318-325 - Test Cost Minimization for Hybrid BIST
Gert Jervan, Zebo Peng, Raimund Ubar
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'2000), Yamanashi, Japan, 25-27 October, 2000, pp. 283-291. - High-level Test Synthesis with Hierarchical Test Generation
Gert Jervan, Petru Eles, Zebo Peng, Jaan Raik, Raimund Ubar
IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 1999, pages 291-296 - A Hierarchical Test Generation Technique for Embedded Systems
Gert Jervan, Petru Eles, Zebo Peng
Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999, pages 21-24 - A Uniform Test Generation Technique for Hardware/Software Systems
Gert Jervan, Petru Eles, Zebo Peng
IEEE European Test Workshop, Constance, Germany, May 25-28, 1999 - Hierarchical Test Generation for Digital Systems
Marina Brik, Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar
Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp. 131-136, 1998. - Hierarchical Test Generation with Multi-Level Decision Diagram Models
Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar
7th IEEE North Atlantic Test Workshop, West Greenwich, RI, USA, pp. 26-33, May 28-29, 1998. - DECIDER: A Decision Diagram based Hierarchical Test Generation System
Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar
DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998.
Project Members
Selected Publications