Linköping University: Students Alumni Trade and Industry/Society Internal Search
NORCHIP99

High-level Test Synthesis with Hierarchical Test Generation

Gert Jervan
 
Petru Eles Author homepage
Zebo Peng Author homepage
 
Jaan Raik
Raimund Ubar

IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 1999, pages 291-296

ABSTRACT
A novel full design and test generation system with combined High-Level Synthesis (HLS) and automated Hierarchical Test Pattern Generation (HTPG) was developed and experimented. The high-level synthesis is based on representation model called Extended Timed Petri Net (ETPN). In the test generator both register-transfer (RT) and gate-level descriptions are used, and Decision diagrams (DD) are exploited as a uniform model for describing systems at both levels. In addition to the synthesis and test generator tools, interfaces to behavioral and RT-level VHDL and EDIF netlist formats have been implemented. In the paper, an overview of the implementation is given and experimental data showing the viability of the approach and the efficiency of respective tools are provided.


Related files:
NORCHIP99.pdfAdobe Acrobat portable document
NORCHIP99.ps.gzpostscript document, compressed (with gzip)

Copyright note for papers published by the IEEE Computer Society:
Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.


[JEPR99] Gert Jervan, Petru Eles, Zebo Peng, Jaan Raik, Raimund Ubar, "High-level Test Synthesis with Hierarchical Test Generation", IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 1999, pages 291-296
( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)