A Hierarchical Test Generation Technique for Embedded Systems
Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999, pages 21-24
ABSTRACT
This paper presents a hierarchical test generation technique for embedded systems containing hardware and software. The technique is applied to the system-level specification of such systems. Different from the traditional approaches, hardware and software parts of an embedded system are handled in a uniform way. We will in particular show how the proposed technique can be applied at high levels of abstraction and how the software domain of the specification can also be successfully covered.
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[JEP99] Gert Jervan, Petru Eles, Zebo Peng, "A Hierarchical Test Generation Technique for Embedded Systems", Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999, pages 21-24 |
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