Access Time Analysis for IEEE P1687
IEEE Transactions on Computers, Oct. 2012, Volume 61, Issue 10, pp 1459-1472.
The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan-chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan-path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e. concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e. network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs.
Copyright note for papers published by the IEEE Computer Society:
Copyright IEEE. Personal use of this material is permitted. However,
permission to reprint/republish this material for advertising or
promotional purposes or for creating new collective works for resale
or redistribution to servers or lists, or to reuse any copyrighted
component of this work in other works, must be obtained from the IEEE.
[GICL12] Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson, "Access Time Analysis for IEEE P1687", IEEE Transactions on Computers, Oct. 2012, Volume 61, Issue 10, pp 1459-1472.