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High-Level and Hierarchical Test Sequence Generation

Gert Jervan Author homepage
Zebo Peng Author homepage
Olga Goloubeva
Matteo Sonza Reorda
Massimo Violante

IEEE International Workshop on High Level Design Validation and Test, Cannes, France, October 27-29, 2002, pp. 169-174

Test generation at the gate-level produces high-quality tests but is computationally expensive in the case of large systems. Recently, several research efforts have investigated the possibility of devising test generation methods and tools to work on high-level descriptions. The goal of these methods is to provide the designers with testability information and test sequences in the early design stages. The cost for generating test sequences in the high abstraction levels is often lower than that for generating test sequences at theIEEE Transactions on VLSI Systems, Vol. 12, No. 8, August 2004, pp. 793-811In this paper we present an approach to mapping and scheduling of distributed embedded systems for hard real-time applications, aiming at a minimization of the system modification cost. We consider an incremental design process that starts from an already existing system running a set of applications. We are interested to implement new functionality such that the timing requirements are fulfilled, and the following two requirements are also satisfied: the already running applications are disturbed as little as possible, and there is a good chance that, later, new functionality can easily be added to the resulted system. Thus, we propose a heuristic which finds the set of already running applications which have to be remapped and rescheduled at the same time with mapping and scheduling the new application, such that the disturbance on the running system (expressed as the total cost implied by the modifications) is minimized. Once this set of applications has been determined, we outline a mapping and scheduling algorithm aimed at fulfilling the requirements stated above. The approaches have been evaluated based on extensive experiments using a large number of generated benchmarks as well as a real-life example.

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[JPGS02] Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante, "High-Level and Hierarchical Test Sequence Generation", IEEE International Workshop on High Level Design Validation and Test, Cannes, France, October 27-29, 2002, pp. 169-174
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