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Core Based SOC Testing Using Functional Connections

Project Description

The main focus of this project is to develop methods for transportation and control of tests in System-On-Chip (SOC) designs. The main objective is to develop a test access methodology that reuses functional connections, e.g. busses or networks. The reason for this is to decrease the routing overhead. Additional buffers may be necessary in order to have concurrent application of the tests. Another property that is considered is the implementation of a test-controller used for directing the transmission of tests. In this project we propose a technique that deals with the test scheduling problem with this new properties while minimising the test-controller and buffer size for a multi-core SOC.

    Project Members

    Selected Publications