Linköping University: Students Alumni Trade and Industry/Society Internal Search
anlar_ats08

Core-Level Expansion of Compressed Test Patterns

Anders Larsson
 
Xin Zhang
Erik Larsson
 
Krishnendu Chakrabarty

17th Asian Test Symposium (ATS), Sapporo, JAPAN, November 24-27, 2008, pp. 277-282.

ABSTRACT
The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.


Related files:
anlar_ats08.pdfAdobe Acrobat portable document


[LZLC08] Anders Larsson, Xin Zhang, Erik Larsson, Krishnendu Chakrabarty, "Core-Level Expansion of Compressed Test Patterns", 17th Asian Test Symposium (ATS), Sapporo, JAPAN, November 24-27, 2008, pp. 277-282.
( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)