Linköping University: Students Alumni Trade and Industry/Society Internal Search

Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation

Nima Aghaee
Zhiyuan He
Zebo Peng Author homepage
Petru Eles Author homepage

19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.

Systems on Chip implemented with deep submicron technologies suffer from two undesirable effects, high power density, thus high temperature, and high process variation, which must be addressed in the test process. This paper presents two temperature-aware scheduling approaches to maximize the test throughput in the presence of inter-chip process variation. The first approach, an off-line technique, improves the test throughput by extending the traditional scheduling method. The second approach, a hybrid one, improves further the test throughput with a chip classification scheme at test time based on the reading of a temperature sensor. Experimental results have demonstrated the efficiency of the proposed methods.

Related files:
nimag_ATS10.pdfAdobe Acrobat portable document

Copyright note for papers published by the IEEE Computer Society:
Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.

[AHPE10] Nima Aghaee, Zhiyuan He, Zebo Peng, Petru Eles, "Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation", 19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.
( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)