SYDIC-Training Course on
System-Level Design of Embedded Systems
Part I: Lectures
Lecture 1: Introduction (2 hours)
- Embedded systems and their design
- Characteristics and requirements
Lecture 2: Models of computation and specification languages (5 hours)
- System specification and formal methods
- Models of computation
- Dataflow models
- Petri nets
- Discrete event models
- Synchronous finite state machines & synchronous languages
- Codesign finite state machines & the POLIS system
- Timed automata
- What modeling approach and specification language to choose?
Lecture 3: Embedded system architectures (3 hours)
- Component and platform-based design
- Architecture specialization techniques
- Typical architectures for embedded systems
- Design space exploration
Lecture 4: Real-time embedded systems: task scheduling (3 hours)
- Real-time systems and their typical features
- Worst-case execution time analysis
- Task scheduling policies
- Static cyclic scheduling
- Priority based scheduling
- Schedulability analysis
Lecture 5: System-level power/energy optimization (3 hours)
- Sources of power dissipation
- System level power optimization
- Dynamic power management
- Mapping and scheduling for low energy
- Real-time scheduling with dynamic voltage scaling
Main literature:
- Ahmed A. Jerraya, Jean Mermet, editors: "System-Level Synthesis," Kluwer Academic Publishers, 1999.
- Lecture notes.
- Selected papers.