SYDIC-Training Course on
Digital Systems Testing and Design for Testability
Part I: Lectures
Lecture 1: Introduction and fault modeling and simulation
- General introduction
- Fault modeling
- Logical level fault modeling; Fault equivalence and fault dominance; RT and high level fault models
- Fault simulation
- Test cost trade-offs
Lecture 2: Automatic test pattern generation (ATPG)
- Basic theory of testing and test pattern generation
- Boolean Derivatives; BDD and design modeling
- Test pattern generation methods
- Gate-level test generation; D-Algorithm; Basic idea of PODEM; Functional test generation; Hierarchical test generation techniques
- Test generation of sequential circuits
Lecture 3: Design for testability
- Basic principles
- Ad hoc solution, including test point insertion
- Scan techniques, theory and practice
- Partial scan selection
Lecture 4: Test synthesis and related issues
- Testability analysis techniques
- High-level test synthesis
- Board and system level test issues
- Core-based SoC test
- Test scheduling; Test infrastructure design; Test power management
- Advanced issues
Lecture 5: Built-in self-test
- Generic requirements for BIST
- Theory of pseudo-random generation as tests
- Response compression
- Special BIST Architectures
- Hybrid BIST and its optimization
Lecture 6: Testability issues in hardware/software systems
- Heterogeneous systems and their design process
- Design validation and formal verification
- Design validation by model execution - design testing
- Levels of testing; Functional vs. structural testing; Path testing; Transaction flow testing; Data-flow testing; Transition testing; Mutation testing; Testability metrics
- Hardware/software co-design for testability
Main literature:
- Principles of Testing Electronic Systems, Samiha Mourad, Yervant Zorian, ISBN: 0-471-31931-7, John Wiley & Sons, 2000.
- Lecture notes.
- Selected papers.