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Call for Participation in a SYDIC-Training Course on

Digital Systems Testing and Design for Testability

Objective

To study the basic principles and practice of test technology and design-for-testability methods for digital systems. To address also issues related to the integration of test consideration with system synthesis and to system-on-chip testing.

Target Audience

Designers and test engineers interested in hardware testing and design for testability techniques for digital systems.

Course Contents

  • Fault modeling and simulation.
  • Automatic test pattern generation.
  • Basic principles of design for testability.
  • Testability analysis.
  • Testability enhancement techniques.
  • Test synthesis.
  • Testability issues in hardware/software systems.
  • Built-in self-test and special BIST architectures.

Course Organization

Schedule

  • Wednesday, March 3
        08:30-09:00 Registration and coffee
        09:00-18:00 Lecture
  • Thursday, March 4
        09:00-18:00 Lecture
  • Friday, March 5
        09:00-17:00 Lab exercise

Download the course flyer here!

 When
March 3-5, 2004
(cancelled)
Where
Conference room "Donald Knuth,"
Linköping University
Organizer
Prof. Zebo Peng
Embedded Systems Lab
Course Fee

Free for participants from partners' organisations
(Please contact Prof. Zebo Peng for further information).

Others: 10 000 SEK for the whole course, 7 000 SEK for the lecture part
Register Now!

Online

Offline

 

The course is given in the framework of the EU project IST-2001-35100 SYDIC-Training