Digital Systems Testing and Design for Testability

The lab exercise is intended to give some hands-on experience with commercial test and design for testability (DFT) tools. We will illustrate the features of such tools and show their placement with respect to the overall design flow. The exercises are performed with Mentor Graphics FastScan ATPG tool suite.

The first part of the exercise concentrates on test pattern generation and fault simulation. These concepts will be illustrated based on realistic design examples. The exercise will also illustrate how these tools fit into the overall design flow.

The second part of the exercise deals with design for testability. In particular, one of the mainstream DFT technologies - scan insertion - will be used in the exercise. We will study the practical aspects of scan insertion and learn how test generation can efficiently be performed for scanned circuits.