- Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
Swedish System-on-Chip Conference (SSoCC'05), Tammsvik, Stockholm, Sweden, April 18-19, 2005 (Informal Digest)
- An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture
Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng
Swedish System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004 (Informal Digest)
- High-Level and Hierarchical Test Sequence Generation
Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante
Swedish System-on-Chip Conference (SSoCC'03), Sunbyholms Slott, Eskilstuna, Sweden, April 8-9, 2003 (Informal Digest)
- Report D1: Report on benchmark identification and planning of experiments to be performed
Gert Jervan, Zebo Peng, Matteo Sonza Reorda, Massimo Violante
COTEST Project Report, Politecnico di Torino, Linköping University, 2002.
- Report D4: Final Report on Project Results
Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante, Petru Eles, Gert Jervan, Zebo Peng
COTEST Project Report, Politecnico di Torino, Linköping University, 2002.
- Report D5: Report on Dissemination Plan
Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante, Petru Eles, Gert Jervan, Zebo Peng
COTEST Project Report, Politecnico di Torino, Linköping University, 2002.
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