SSOCC04_gerje

An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture

Raimund Ubar
 
Maksim Jenihhin
Gert Jervan Author homepage
 
Zebo Peng Author homepage

Swedish System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004 (Informal Digest)

ABSTRACT
This paper presents an approach to the test time minimization problem for parallel hybrid BIST with test pattern broadcasting in core-based systems. The hybrid test set is assembled from pseudorandom test patterns that are generated online and deterministic test patterns that are generated off-line and stored in the system. The pseudorandom patterns are broadcasted and applied to all cores in parallel. The deterministic patterns are, on the other hand, generated for particular cores, one at a time, but applied (broadcasted) in parallel to all other cores and used for the rest of the system as pseudorandom patterns. We propose an iterative algorithm to find the optimal combination between those two test sets under given memory constraints, so that the systems testing time is minimized. Our approach employs a fast cost estimation method in order to avoid exhaustive search and to speed-up the optimization process. Experimental results have shown the efficiency of the algorithm to find a near-optimal solution with very few iterations.


[UJJP04] Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng, "An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture", Swedish System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004 (Informal Digest)
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