Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip
17th Asian Test Symposium (ATS), Sapporo, JAPAN, November 24-27, 2008, pp. 283-288.
Thermal safety has become a major challenge to the testing of systems-on-chip with deep sub-micron technologies. In order to avoid overheating the devices under test while reducing test application times, new techniques are needed. In this paper, we propose a test scheduling technique to minimize the test application time such that the temperatures of individual cores are kept below a given limit. The proposed approach takes into account thermal influences between cores, and thus accurate temperature evolution information of all cores in a system-on-chip is needed for the test scheduling. In order to avoid overheating, we have employed a thermal simulation driven scheduling algorithm, in which instantaneous thermal simulation results are used to guide the partitioning of test sets into test sub-sequences and to determine cooling periods inserted between the partitions. Furthermore, the partitioned test sets for different cores are interleaved such that a cooling period reserved for one core can be utilized for the test-data transportations and test applications for other cores. Experimental results have shown that by using the proposed technique, the test application time is minimized and the temperatures of cores under test are kept below the temperature limit during the entire test process.
[HPE08] Zhiyuan He, Zebo Peng, Petru Eles, "Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip", 17th Asian Test Symposium (ATS), Sapporo, JAPAN, November 24-27, 2008, pp. 283-288.