Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation
19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.
Systems on Chip implemented with deep submicron technologies suffer from two undesirable effects, high power density, thus high temperature, and high process variation, which must be addressed in the test process. This paper presents two temperature-aware scheduling approaches to maximize the test throughput in the presence of inter-chip process variation. The first approach, an off-line technique, improves the test throughput by extending the traditional scheduling method. The second approach, a hybrid one, improves further the test throughput with a chip classification scheme at test time based on the reading of a temperature sensor. Experimental results have demonstrated the efficiency of the proposed methods.
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[AHPE10] Nima Aghaee, Zhiyuan He, Zebo Peng, Petru Eles, "Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation", 19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.