erila_vlsi_soc05

Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint

Erik Larsson Author homepage
 
Stina Edbom

IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip (IFIP VLSI-SOC) 2005, Perth, Australia, October 17-19, 2005, pp. 429-434

ABSTRACT
The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automatic Test Equipment) memory. In this paper, we (1) define a test quality metric based on fault coverage, defect probability and number of applied test vectors, and (2) a test data truncation scheme. The truncation scheme combines (1) test data (vector) selection for each core based on our metric, and (2) scheduling of the execution of the selected test data, in such a way that the system test quality is maximized, while the selected test data is guaranteed to fit the ATEs memory. We have implemented the technique and the experimental results, produced at reasonable CPU times, on several ITC02 benchmarks show that high test quality can be achieved by a careful selection of test data.


Related files:
erila_vlsi_soc05.final.pdf, Adobe Acrobat portable document


[LE05] Erik Larsson, Stina Edbom, "Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint", IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip (IFIP VLSI-SOC) 2005, Perth, Australia, October 17-19, 2005, pp. 429-434
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