Master Thesis by
Department of Computer and Information Science
Linköping University, Sweden
Testing is used to ensure the correct functionality of a manufactured chip. During testing, test data (a set of test vectors) is applied as input to the chip and the test response (the output) is compared to the expected one. If the test is passed, the chip is assumed to be fault-free.
The increasing complexity of integrated systems will lead to an increasing amount of data needed for testing. As the amount of test data will increase, the memory size of the test equipment will be a limitation and the test data needs to be reduced in order to fit the tester's memory. In a core-based environment, where several cores are integrated on one single chip, each core is tested with a dedicated set of test vectors. It is usually the case that the first test vectors in a set detect more faults than the last test vectors and that the probability of a defect is varying between cores.
By reducing the amount of test data we lower the test application time but also the quality of the test. Therefore the reduction need to be done in such a way that the quality of the test is maximized. The quality of testing is highly related to the number of faults that can be detected during the testing, the number of used test vectors and the probability that a defect will appear in a testable unit. We assume that the defect probabilities are collected from the production line and are known prior to scheduling, and we introduce the assumption that the fault detection (fault coverage) can be estimated to an exponential function.
In this thesis we propose two test scheduling techniques which reduce the amount of test data in order to meet the time constraint caused by the ATE memory depth. The first technique is a sequential technique based on test ordering, while the second one selects the number of test vectors for each core, and schedules the selected test vectors in such a way that the probability to find defects under a given time constraint is maximized. We have implemented our techniques and experiments show that we can achieve high test quality while lowering the test application time.