Formal Verification of Embedded Systems in a Reuse Methodology

Project Description

This project aims at developing a methodology for formal verification in a context where the system model consist of predesigned components. These components have already been verified by their providers and are assumed to be correct. An important issue is to develop a method how to take advantage of this fact in order to reduce verification time. Another related issue is how to model the environment in which the components are placed.

Project Members

• Petru Eles, contact person
• Zebo Peng
• Daniel Karlsson

Selected Publications

• Transactor-based Formal Verification of Real-time Embedded Systems
  Daniel Karlsson, Petru Eles, Zebo Peng
  In Lecture Notes in Electrical Engineering, Vol. 10, Ed.: E. Villar, Springer.
• Model Validation for Embedded Systems Using Formal Method-Aided Simulation
  Daniel Karlsson, Petru Eles, Zebo Peng
  IET Computers & Digital Techniques journal, Vol. 2, Number 6, November 2008, pp. 413-433.
• Transactor-based Formal Verification of Real-time Embedded Systems
  Daniel Karlsson, Petru Eles, Zebo Peng
  Forum on Specification & Design Languages (FDL), Barcelona, Spain, September 18-20, 2007.
• What Impacts Course Evaluation?
  Erik Larsson, Medhi Amirijoo, Daniel Karlsson, Petru Eles
  12th SIGCSE Conf. on Innovation and Technology in Computer Science Education, Dundee, Scotland, UK, June 25-27, 2007, pp. 333-333.
• Verification of Component-based Embedded System Designs
  Daniel Karlsson
  Ph. D. Thesis No. 1017, Dept. of Computer and Information Science, Linköping University, June 2006 (Opponent: Prof. Bashir Al-Hashimi, University of Southampton, UK)
• Formal Verification of Component-based Designs
  Daniel Karlsson, Petru Eles, Zebo Peng
  Journal of Design Automation for Embedded Systems, Vol. 11, No. 1, March 2007, pp. 49-90
• Formal Verification of SystemC Designs Using a Petri-Net based Representation
  Daniel Karlsson, Petru Eles, Zebo Peng
  Design Automation and Test in Europe Conference (DATE 2006), Munich, Germany, March 6-10, 2006, pp. 1228-1233
• Validation of Embedded Systems using Formal Method aided Verification
  Daniel Karlsson, Petru Eles, Zebo Peng
  8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, 2005, pp. 196-199
• Validation of Embedded Systems using Formal Method aided Simulation
  Daniel Karlsson, Petru Eles, Zebo Peng
  Swedish System-on-Chip Conference (SSoCC'05), Tammsvik, Stockholm, Sweden, April 18-19, 2005 (Informal Digest)
• A Formal Verification Approach for IP-based Designs
  Daniel Karlsson, Petru Eles, Zebo Peng
  Forum on Specification and Design Languages, Lille, France, September 13-17, 2004, pp. 556-567
• A Formal Verification Methodology for IP-based Designs
  Daniel Karlsson, Petru Eles, Zebo Peng
  EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools, Rennes, France, August 31-September 3, 2004, pp 372-379.
• A Formal Verification Methodology for IP-based Designs
  Daniel Karlsson, Petru Eles, Zebo Peng
  Swedish System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004 (Informal Digest)
• Towards Formal Verification in a Component-based Reuse Methodology
  Daniel Karlsson
  Licentiate Thesis No. 1058, Dept. of Computer and Information Science, Linköping University, December 2003
• Automatic Generation of a Formal Verification Bench for a Reuse Methodology
  Daniel Karlsson, Petru Eles, Zebo Peng
  Swedish System-on-Chip Conference (SSoCC'03), Sunbyholms Slott, Eskilstuna, Sweden, April 8-9, 2003 (Informal Digest)
• Formal Verification in a Component-based Reuse Methodology
  Daniel Karlsson, Petru Eles, Zebo Peng
  International Symposium on System Synthesis (ISSS) 2002, Kyoto, Japan, October 2-4, 2002, pp. 156-161
• A Front End to a Java Based Environment for the Design of Embedded Systems
  Daniel Karlsson, Petru Eles, Zebo Peng
  4th IEEE DDECS Workshop, Gyor, Hungary, April 2001, pp. 71-78

Last modified on Sunday January 11, 2004 by Owner's name