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Formal Verification of Embedded Systems in a Reuse Methodology

Project Description

This project aims at developing a methodology for formal verification in a context where the system model consist of predesigned components. These components have already been verified by their providers and are assumed to be correct. An important issue is to develop a method how to take advantage of this fact in order to reduce verification time. Another related issue is how to model the environment in which the components are placed.

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    Selected Publications