Formal Verification of SystemC Designs Using a Petri-Net based Representation
Design Automation and Test in Europe Conference (DATE 2006), Munich, Germany, March 6-10, 2006, pp. 1228-1233
ABSTRACT
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed temporal logic. The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments.
[KEP06] Daniel Karlsson, Petru Eles, Zebo Peng, "Formal Verification of SystemC Designs Using a Petri-Net based Representation", Design Automation and Test in Europe Conference (DATE 2006), Munich, Germany, March 6-10, 2006, pp. 1228-1233 |
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