Defect Probability-based System-On-Chip Test Scheduling
6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, Poland, April 14-16, 2003, pp. 25-32
ABSTRACT
In this paper we address the test scheduling problem for system-on-chip. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test set in order to schedule the test sets so that the expected total test time will be minimized. It supports different test bus structures, test scheduling strategies (sequential scheduling vs. concurrent scheduling), and test set assumptions (fixed test time vs. flexible test time). Several heuristic algorithms have been developed and experiments performed to demonstrate their efficiency.
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[LPP03] Erik Larsson, Julien Pouget, Zebo Peng, "Defect Probability-based System-On-Chip Test Scheduling", 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, Poland, April 14-16, 2003, pp. 25-32 |
