Process-variation and Temperature Aware SoC Test Scheduling Technique
Journal of Electronic Testing: Theory and Applications, Aug. 2013, Volume 29, Issue 4, pp. 499-520.
ABSTRACT
High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoCs). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC’02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.
[APE13] Nima Aghaee, Zebo Peng, Petru Eles, "Process-variation and Temperature Aware SoC Test Scheduling Technique", Journal of Electronic Testing: Theory and Applications, Aug. 2013, Volume 29, Issue 4, pp. 499-520. |
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