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Final Program


19:30 - RECEPTION (At the conference venue)


8:45 - 9:00 OPENING

9:00 - 10:00 KEYNOTE

Chair: Alex Orailoglu, University of California, San Diego, USA

Future Challenges in Embedded Systems
Andrea Cuomo, Corporate Vice President, General Manager Advanced System Technology, STMicroelectronics

10:00 - 10:30 BREAK

10:30 - 12:15 SESSION A1 (12:00 - 12:15 poster session and break)

Special session: Organic Computing
Chairs: Per Bjureus, SaabTech AB, Sweden; Joerg Henkel, University of Karlsruhe, Germany

Organic Computing - On the Feasibility of Controlled Emergence
C. Müller-Schloer, Universität Hannover

Organic Control Architectures for Ubiquitous Systems
Paul Lukowicz, UMIT-University for Health Informatics and Technology Tyrol

Towards Self-Organizing Computing Systems – System-Wide Monitoring and Adaption
Wolfgang Karl, Universität Karlsruhe

10:30 - 12:15 SESSION B1 (11:45 - 12:15 poster session and break)

New Design Techniques for Application Specific Processors
Chairs: Catherine Gebotys, University of Waterloo, Canada; Soonhoi Ha, Seoul National University, Korea

A Loop Accelerator for Low Power Embedded VLIW Processors (best paper candidate)
Binu Mathew, Al Davis - University of Utah, USA

Dual-Pipeline Heterogeneous ASIP Design
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran - University of New South Wales, Australia

Fast Cycle-Accurate Simulation and Instruction Set Generation for Constraint-Based Descriptions of Programmable Architectures
Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Kurt Keutzer - University of California, Berkeley, USA
Christian Sauer - Infineon Technologies, Germany

12:15 - 15:00 LUNCH (At Stockholm City Hall : map)

15:00 - 17:30 SESSION A2 (16:40 - 17:30 poster session and break)

Advances in Software and Hardware Synthesis Techniques for DSP applications
Chairs: Miguel Miranda, IMEC, Belgium; Robert Walker, Kent State University, USA

Hardware Synthesis From Coarse-Grained Dataflow Specification For Fast HW/SW Cosynthesis
Hyunuk Jung and Soonhoi Ha - Seoul National University, Korea

Efficient Mapping of Hierarchical Trees on Coarse-Grain Reconfigurable Architectures
F. Rivera, M. Sanchez-Elez, M. Fernandez, R. Hermida  - Universidad Complutense, Madrid, Spain,
N. Bagherzadeh - University of California, Irvine, USA

Detecting overflow detection
Vladimir Kotlyar, Mayan Moudgill - Sandbridge Technologies, Inc., USA

Memory Accesses Management During High Level Synthesis
Gwenole Corre, Eric Senn, Nathalie Julien, Pierre Bomel, Eric Martin - LESTER/University of South Brittany, France

15:00 - 17:30 SESSION B2 (16:40 - 17:30 poster session and break)

Multiprocessor SoC: Design Strategies and Programming Models
Chairs: Luciano Lavagno, Politecnico Torino, Italy; Paul Pop, Linkoping University, Sweden

Parallel Programming Models for a Multi-Processor SoC Platform Applied to High-Speed Traffic Management (best paper candidate)
Pierre Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane - Central R&D, STMicroelectronics, Ottawa, Canada
Gabriela Nicolescu - Ecole Polytechnique de Montreal, Canada

Benchmark-Based Design Strategies for Single Chip Heterogeneous Multiprocessors
JoAnn M Paul, Donald E Thomas, Alex Bobrek - Carnegie Mellon University, USA

Automatic Synthesis of System on Chip Multiprocessor Architectures for Process Networks
Basant Kumar Dwivedi, Anshul Kumar and M. Balakrishnan - Indian Institute of Technology Delhi, India

Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation
Xinping Zhu, Wei Qin, Sharad Malik - Princeton University, USA

17:30 - 19:00: PANEL 1

Secure and safety critical vs. insecure, non-safety critical embedded systems: Do they require completely different design approaches?
Organizer: Peter Marwedel University of Dortmund, Germany
Moderator: Catherine Gebotys University of Waterloo, Canada

Jakob Axelsson - Volvo Car Corporation, Sweden
Marco Bekooij - Philips, The Netherlands
Francky Catthoor - K.U. Leuven and IMEC, Belgium
Rolf Ernst - Technical University Braunschweig, Germany
Pierre Paradinas - CNAM, France


8:15 - 9:15 KEYNOTE

Chair: Pai H. Chou, University of California, Irvine, USA

Cellular handset technology system requirements and integration trends
Sven Mattisson - Senior Expert - Strategic Product Management, Ericsson Mobile Platforms AB, Lund, Sweden

9:15 - 9:45 BREAK

9:45 - 12:15 SESSION A3 (11:25 - 12:15 poster session and break)

New Modeling Approaches and their Application
Chairs: Dan Gajski, University of California, Irvine, USA; Yukihiro Nakamura, Kyoto University, Japan

Transaction Level Modeling: Flows and Use Models
Adam Donlin - Xilinx Research Labs, San Jose, USA

Exploiting Polymorphism in HW Design: A Case Study in the ATM Domain
Luigi Pomante - CEFRIEL, Milano, Italy

Facilitating Reuse in Hardware Models with Enhanced Type Inference
Manish Vachharajani, Neil Vachharajani, David August, and Sharad Malik - Princeton University, USA

System-On-Chip Validation using UML and CWL
Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata, - Fujitsu, Japan

9:45 - 12:15 SESSION B3 (11:00 - 12:15 poster session and break)

Energy-Aware Compiling and Scheduling
Chairs: Nikil Dutt, University of California, Irvine, USA; Donatella Sciuto, Politecnico di Milano, Italy

Compiler-Directed Code Restructuring for Reducing Data TLB Energy
M. Kandemir, G. Chen - The Pennsylvania State University, USA,  I. Kadayif - Canakkale Onsekiz Mart University, Turkey

Dynamic Overlay of Scratchpad Memory for Energy Minimization
Manish Verma, Lars Wehmeyer, Peter Marwedel - University of Dortmund, Germany

CPU Scheduling for Statistically-Assured Real-Time Performance and Improved Energy Efficiency
Haisang Wu, Binoy Ravindran, Peng Li -  Virginia Tech, USA,
E. Douglas Jensen - The MITRE Corporation, USA

12:15 - 13:45 LUNCH

13:45 - 15:45 SESSION A4 (15:00 - 15:45 poster session and break)

System-Level Design Space Exploration for Hardware-Software Partitioning and Platform Instantiation
Chairs: Kris Kuchcinski, Lund University, Sweden; Don Thomas, Carnegie Mellon University, USA

Power-Performance Trade-Offs for Reconfigurable Computing
Juanjo Noguera - Hewlett-Packard, Barcelona, Spain,
Rosa M. Badia - Technical University of Catalonia, Spain

Efficient search space exploration for HW-SW partitioning
Sudarshan Banerjee and Nikil Dutt - University of California, USA

Tuning SoC Platforms for Multimedia Processing: Limits and Tradeoffs
Alexander Maxiaguine - ETH Zurich, Switzerland
Yongxin Zhu, Samarjit Chakraborty and Weng-Fai Wong - National University of Singapore

13:45 - 15:45 SESSION B4 (15:00 - 15:45 poster session and break)

Estimation and Design Techniques for Energy-Efficient Memory Systems
Chairs: Peter Marwedel, University of Dortmund, Germany; Pieter van der Wolf, Philips Research, The Netherlands

Energy-Efficient Flash-Memory Storage Systems with an Interrupt-Emulation Mechanism
Chin-Hsien Wu, Tei-Wei Kuo, and Chia-Lin Yang - National Taiwan University,Taiwan

Memory System Design Space Exploration for Low-Power, Real-Time Speech Recognition
Rajeev Krishna, Scott Mahlke, and Todd Austin - University of Michigan, Ann Arbor, USA

Analytical Models for Leakage Power Estimation of Memory Array Structures
Mahesh Mamidipaka, Nikil Dutt - University of California, Irvine, USA,
Kamal Khouri, Magdy Abadir - Freescale/Motorola, Inc., USA

15:45 - 17:45 SESSION A5 (17:00 - 17:45 poster session and break)

Advances in Hardware/Software Co-simulation Techniques
Chairs: Wolfgang Rosenstiel, University of Tuebingen, Germany; Kazutoshi Wakabayashi, NEC, Japan

A Timing-Accurate HW/SW Co-simulation of an ISS with SystemC
Luca Formaggio, Franco Fummi, Graziano Pravadelli - Universita di Verona, Italy

RTOS-Centric Hardware/Software Cosimulator for Embedded System Design
Shinya Honda, Takayuki Wakabayashi - Toyohashi University of Technology, Japan, Hiroyuki Tomiyama, Hiroaki Takada -Nagoya University, Japan

Fast Co-simulation of Transformative Systems with OS Support on SMP Computer
Zhengting He, Aloysius Mok - University of Texas-Austin, USA

15:45 - 17:45 SESSION B5 (17:00 - 17:45 poster session and break)

NoC Design and Optimisation
Chairs: Sri Parameswaran, University of South Wales, Australia; Zebo Peng, Linkoping University, Sweden

Power-Aware Communication Optimization for Networks-on-Chips with Voltage Scalable Links (best paper candidate)
Dongkun Shin and Jihong Kim - Seoul National University, Korea

Reducing Power and Latency in 2-D Mesh NoCs using Globally Pseudochronous Locally Synchronous Clocking
Erland Nilsson, Johnny Öberg - Royal Institute of Technology, Sweden

Multi-objective Mapping for Mesh-based NoC Architectures
Maurizio Palesi, Vincenzo Catania, Giuseppe Ascia - University of Catania, Italy

19:00 -  CONFERENCE DINNER (Restaurant Hasselbacken : map)


08:15 - 10:00 SESSION A6 (09:30 - 10:00 poster session and break)

Software and Hardware Techniques for Performance Optimisation of Embedded Applications
Chairs: Bashir M Al-Hashimi, University of Southampton, UK; Mattias O'Nils, Mid Sweden University, Sweden

Optimizing the memory bandwidth with loop fusion
P. Marchal, F. Catthoor - IMEC, Belgium,
I. Gomez - Universidad Complutense, Madrid, Spain

Operation Tables for Scheduling in the presence of Incomplete Bypassing
Aviral Shrivastava, Nikil Dutt, Alex Nicolau - University of California, Irvine, USA
Eugene Earlie - Intel Labs, Hudson, USA

A Novel Deadlock Avoidance Algorithm and its Hardware Implementation
Jaehwan Lee and Vincent Mooney - Georgia Institute of Technology, USA

08:15 - 10:00 SESSION B6 (09:45 - 10:00 poster session and break)

Special Session: Design and Programming of Embedded Multiprocessors: An Interface-Centric Approach
Chairs: Franco Fummi, University of Verone, Italy; JoAnn Paul, Carnegie Mellon University, USA

TTL: A Task-Level Interface for Modeling and Implementing Parallel Systems
Pieter van der Wolf - Philips Research, The Netherlands

Mapping of Parallel Applications onto Embedded Multi-Processors
Erwin de Kock - Philips Research, The Netherlands

TTL Implementation on an Embedded Multi-DSP
Tomas Henriksson - Philips Research, The Netherlands

TTL Implementation in a Smart Imaging Multi-Processor
Wido Kruijtzer - Philips Research The Netherlands

10:00 - 12:00 SESSION A7 (11:15 - 12:00 poster session and break)

New Techniques for Security and Reliability Enhancement in Embedded Systems
Chairs: Rolf Ernst, Technical University Braunschweig, Germany; Anshul Kumar, Indian Institute of Technology, Delhi, India

Current Flattening in Software and Hardware for Security Applications
Radu Muresan - University of Guelph, Canada,
Catherine Gebotys - University of Waterloo, Canada

Low Energy Security Optimization in Embedded Cryptographic Systems
Catherine Gebotys - University of Waterloo, Canada

Analyzing Heap Error Behavior in Embedded JVM Environments
G. Chen, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin - The Pennsylvania State University, USA

10:00 - 12:00 SESSION B7 (11:15 - 12:00 poster session and break)

On-Chip Communication Architectures: Analysis and Optimisation
Chairs: Farydon Karim, ST Microelectronics, USA; Jonas Plantin, Ericsson, Sweden

Power analysis of system-level on-chip communication architectures
Kanishka Lahiri, Anand Raghunathan - NEC labs, USA

Fast Exploration of Bus-based On-chip Communication Architectures
Sudeep Pasricha, Nikil Dutt - University of California, Irvine, USA,
Mohamed Ben-Romdhane - Conexant Systems, Inc., USA

Efficient Exploration of On-Chip Bus Architectures and Memory Allocation
Sungchen Kim, Chaeseok Im, Soonhoi Ha - Seoul National University, Korea

12:00 - 13:30 PANEL 2

Embedded systems education: How to teach the required skills?
Organizer: Peter Marwedel University of Dortmund, Germany
Moderator: Wolfgang Rosenstiel University of Tuebingen, Germany

Erwin de Kock - Philips Research, The Netherlands
Hugo De Man - K.U. Leuven and IMEC, Belgium
Daniel Gajski - University of California, Irvine, USA
Peter Marwedel - University of Dortmund, Germany
Mariagiovanna Sami - Politecnico di Milano, Italy
Ingemar Söderquist - SaabTech AB, Sweden

13:30 - 15:00 Lunch, Best Paper Award, Closing

Organized events

On-site Registration Hours

  • Monday, Sept. 6th
    11:30am - 6:30pm
  • Tuesday, Sept. 7th
    7:30am - 7:00pm
  • Wednesday, Sept. 8th
    7:30am - 7:00pm
  • Thursday, Sept. 9th
    8:00am - 6:00pm
  • Friday, Sept. 10th
    8:00am - 10:00am

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