This package contains semiconductor devices:
Modelica.Electrical.Analog.Semiconductors.Diode
The simple diode is a two pole. It consists of the diode itself and an parallel ohmic resistance R. The diode formula is simple:
v/vt
i = ids ( e - 1).
If the exponent v/vt reaches the limit maxex, the diode characterisic is linearly continued to avoid overflow.
| Name | Default | Description |
|---|---|---|
| Ids | 1 | Saturation current [A] |
| Vt | 1 | Voltage equivalent of temperature (kT/qn) [V] |
| Maxexp | 1 | Max. exponent for linear continuation |
| R | 1 | Parallel ohmic resistance [Ohm] |
model Diode "Simple diode"
extends Modelica.Electrical.Analog.Interfaces.OnePort;
parameter SIunits.Current Ids=1 "Saturation current";
parameter SIunits.Voltage Vt=1
"Voltage equivalent of temperature (kT/qn)";
parameter Real Maxexp(final min=Modelica.Constants.SMALL) = 1
"Max. exponent for linear continuation";
parameter SIunits.Resistance R=1 "Parallel ohmic resistance";
equation
//assert (R <> 0, "R must not be zero");
i = if (v/Vt > Maxexp) then Ids*(exp(Maxexp)*(1 + v/Vt - Maxexp) - 1) + v
/R else Ids*(exp(v/Vt) - 1) + v/R;
end Diode;
Modelica.Electrical.Analog.Semiconductors.PMOS
The PMOS model is a simple model of a p-channel metal-oxide semiconductor FET. It differs slightly from the device used in the SPICE simulator. For more details please care for H. Spiro.
The model does not consider capacitances. A small fixed drain-source resistance is included (to avoid numerical difficulties).
Some typical parameter sets are:
W L Beta Vt K2 K5 DW DL m m A/V^2 V - - m m 50.e-6 8.e-6 .0085 -.15 .41 .839 -3.8e-6 -4.0e-6 20.e-6 6.e-6 .0105 -1.0 .41 .839 -2.5e-6 -2.1e-6 30.e-6 5.e-6 .0059 -.3 .98 1.01 0 -3.9e-6 30.e-6 5.e-6 .0152 -.69 .104 1.1 -.8e-6 -.4e-6 30.e-6 5.e-6 .0163 -.69 .104 1.1 -.8e-6 -.4e-6 30.e-6 5.e-6 .0182 -.69 .086 1.06 -.1e-6 -.6e-6 20.e-6 6.e-6 .0074 -1. .4 .59 0 0
| Name | Default | Description |
|---|---|---|
| W | 50.0e-6 | Width [m] |
| L | 8.0e-6 | Length [m] |
| Beta | 0.0085 | Transconductance parameter [A/(V*V)] |
| Vt | -0.15 | Zero bias threshold voltage [V] |
| K2 | 0.41 | Bulk threshold parameter |
| K5 | 0.839 | Reduction of pinch-off region |
| dW | -3.8e-6 | Narrowing of channel [m] |
| dL | -4.0e-6 | Shortening of channel [m] |
model PMOS "Simple MOS Transistor"
Interfaces.Pin D "Drain";
Interfaces.Pin G "Gate";
Interfaces.Pin S "Source";
Interfaces.Pin B "Bulk";
parameter SIunits.Length W=50.0e-6 "Width";
parameter SIunits.Length L=8.0e-6 "Length";
parameter SIunits.Transconductance Beta=0.0085
"Transconductance parameter";
parameter SIunits.Voltage Vt=-0.15 "Zero bias threshold voltage";
parameter Real K2=0.41 "Bulk threshold parameter";
parameter Real K5=0.839 "Reduction of pinch-off region";
parameter SIunits.Length dW=-3.8e-6 "Narrowing of channel";
parameter SIunits.Length dL=-4.0e-6 "Shortening of channel";
protected
Real v;
Real uds;
Real ubs;
Real ugst;
Real ud;
Real us;
Real id;
equation
//assert (L + dL > 0, "Effective length must be positive");
//assert (W + dW > 0, "Effective width must be positive");
v = Beta*(W + dW)/(L + dL);
ud = if (D.v > S.v) then S.v else D.v;
us = if (D.v > S.v) then D.v else S.v;
uds = ud - us;
ubs = if (B.v < us) then 0 else B.v - us;
ugst = (G.v - us - Vt + K2*ubs)*K5;
id = if (ugst >= 0) then v*uds*1.e-7 else if (ugst < uds) then -v*uds*
(ugst - uds/2 - 1.e-7) else -v*(ugst*ugst/2 - uds*1.e-7);
G.i = 0;
D.i = if (D.v > S.v) then -id else id;
S.i = if (D.v > S.v) then id else -id;
B.i = 0;
end PMOS;
Modelica.Electrical.Analog.Semiconductors.NMOS
The NMos model is a simple model of a n-channel metal-oxide semiconductor FET. It differs slightly from the device used in the SPICE simulator. For more details please care for H. Spiro.
The model does not consider capacitances. A small fixed drain-source resistance is included (to avoid numerical difficulties).
W L Beta Vt K2 K5 DW DL m m A/V^2 V - - m m 12.e-6 4.e-6 .062 -4.5 .24 .61 -1.2e-6 -.9e-6 depletion 60.e-6 3.e-6 .048 .1 .08 .68 -1.2e-6 -.9e-6 enhancement 12.e-6 4.e-6 .0625 -.8 .21 .78 -1.2e-6 -.9e-6 zero 50.e-6 8.e-6 .0299 .24 1.144 .7311 -5.4e-6 -4.e-6 20.e-6 6.e-6 .041 .8 1.144 .7311 -2.5e-6 -1.5e-6 30.e-6 9.e-6 .025 -4. .861 .878 -3.4e-6 -1.74e-6 30.e-6 5.e-6 .031 .6 1.5 .72 0 -3.9e-6 50.e-6 6.e-6 .0414 -3.8 .34 .8 -1.6e-6 -2.e-6 depletion 50.e-6 5.e-6 .03 .37 .23 .86 -1.6e-6 -2.e-6 enhancement 50.e-6 6.e-6 .038 -.9 .23 .707 -1.6e-6 -2.e-6 zero 20.e-6 4.e-6 .06776 .5409 .065 .71 -.8e-6 -.2e-6 20.e-6 4.e-6 .06505 .6209 .065 .71 -.8e-6 -.2e-6 20.e-6 4.e-6 .05365 .6909 .03 .8 -.3e-6 -.2e-6 20.e-6 4.e-6 .05365 .4909 .03 .8 -.3e-6 -.2e-6 12.e-6 4.e-6 .023 -4.5 .29 .6 0 0 depletion 60.e-6 3.e-6 .022 .1 .11 .65 0 0 enhancement 12.e-6 4.e-6 .038 -.8 .33 .6 0 0 zero 20.e-6 6.e-6 .022 .8 1 .66 0 0
| Name | Default | Description |
|---|---|---|
| W | Width [m] | |
| L | Length [m] | |
| Beta | 2.e-5 | Transconductance parameter [A/(V*V)] |
| Vt | 0 | Zero bias threshold voltage [V] |
| K2 | 0 | Bulk threshold parameter |
| K5 | 1 | Reduction of pinch-off region |
| dW | 0 | narrowing of channel [m] |
| dL | 0 | shortening of channel [m] |
model NMOS "Simple MOS Transistor"
Interfaces.Pin D "Drain";
Interfaces.Pin G "Gate";
Interfaces.Pin S "Source";
Interfaces.Pin B "Bulk";
parameter SIunits.Length W "Width";
parameter SIunits.Length L "Length";
parameter SIunits.Transconductance Beta=2.e-5
"Transconductance parameter";
parameter SIunits.Voltage Vt=0 "Zero bias threshold voltage";
parameter Real K2=0 "Bulk threshold parameter";
parameter Real K5=1 "Reduction of pinch-off region";
parameter SIunits.Length dW=0 "narrowing of channel";
parameter SIunits.Length dL=0 "shortening of channel";
protected
Real v;
Real uds;
Real ubs;
Real ugst;
Real ud;
Real us;
Real id;
equation
//assert (L + dL > 0, "Effective length must be positive");
//assert (W + dW > 0, "Effective width must be positive");
v = Beta*(W + dW)/(L + dL);
ud = if (D.v < S.v) then S.v else D.v;
us = if (D.v < S.v) then D.v else S.v;
uds = ud - us;
ubs = if (B.v > us) then 0 else B.v - us;
ugst = (G.v - us - Vt + K2*ubs)*K5;
id = if (ugst <= 0) then v*uds*1.e-7 else if (ugst > uds) then v*uds*(
ugst - uds/2 + 1.e-7) else v*(ugst*ugst/2 + uds*1.e-7);
G.i = 0;
D.i = if (D.v < S.v) then -id else id;
S.i = if (D.v < S.v) then id else -id;
B.i = 0;
end NMOS;
Modelica.Electrical.Analog.Semiconductors.NPN
This model is a simple model of a bipolar npn junction transistor according to Ebers-Moll.
A typical parameter set is:
Bf Br Is Vak Tauf Taur Ccs Cje Cjc Phie Me PHic Mc Gbc Gbe Vt - - A V s s F F F V - V - mS mS V 50 0.1 1e-16 0.02 0.12e-9 5e-9 1e-12 0.4e-12 0.5e-12 0.8 0.4 0.8 0.333 1e-15 1e-15 0.02585
| Name | Default | Description |
|---|---|---|
| Bf | 50 | Forward beta |
| Br | 0.1 | Reverse beta |
| Is | 1.e-16 | Transport saturation current [A] |
| Vak | 0.02 | Early voltage (inverse), 1/Volt [1/V] |
| Tauf | 0.12e-9 | Ideal forward transit time [s] |
| Taur | 5e-9 | Ideal reverse transit time [s] |
| Ccs | 1e-12 | Collector-substrat(ground) cap. [F] |
| Cje | 0.4e-12 | Base-emitter zero bias depletion cap. [F] |
| Cjc | 0.5e-12 | Base-coll. zero bias depletion cap. [F] |
| Phie | 0.8 | Base-emitter diffusion voltage [V] |
| Me | 0.4 | Base-emitter gradation exponent |
| Phic | 0.8 | Base-collector diffusion voltage [V] |
| Mc | 0.333 | Base-collector gradation exponent |
| Gbc | 1e-15 | Base-collector conductance [S] |
| Gbe | 1e-15 | Base-emitter conductance [S] |
| Vt | 0.02585 | Voltage equivalent of temperature [V] |
| EMin | -100 | if x < EMin, the exp(x) function is linearized |
| EMax | 40 | if x > EMax, the exp(x) function is linearized |
model NPN "Simple BJT according to Ebers-Moll"
parameter Real Bf=50 "Forward beta";
parameter Real Br=0.1 "Reverse beta";
parameter SIunits.Current Is=1.e-16 "Transport saturation current"
;
parameter SIunits.InversePotential Vak=0.02
"Early voltage (inverse), 1/Volt";
parameter SIunits.Time Tauf=0.12e-9 "Ideal forward transit time";
parameter SIunits.Time Taur=5e-9 "Ideal reverse transit time";
parameter SIunits.Capacitance Ccs=1e-12
"Collector-substrat(ground) cap.";
parameter SIunits.Capacitance Cje=0.4e-12
"Base-emitter zero bias depletion cap.";
parameter SIunits.Capacitance Cjc=0.5e-12
"Base-coll. zero bias depletion cap.";
parameter SIunits.Voltage Phie=0.8
"Base-emitter diffusion voltage";
parameter Real Me=0.4 "Base-emitter gradation exponent";
parameter SIunits.Voltage Phic=0.8
"Base-collector diffusion voltage";
parameter Real Mc=0.333 "Base-collector gradation exponent";
parameter SIunits.Conductance Gbc=1e-15
"Base-collector conductance";
parameter SIunits.Conductance Gbe=1e-15 "Base-emitter conductance"
;
parameter SIunits.Voltage Vt=0.02585
"Voltage equivalent of temperature";
parameter Real EMin=-100
"if x < EMin, the exp(x) function is linearized";
parameter Real EMax=40
"if x > EMax, the exp(x) function is linearized";
protected
Real vbc;
Real vbe;
Real qbk;
Real ibc;
Real ibe;
Real cbc;
Real cbe;
Real ExMin;
Real ExMax;
Real Capcje;
Real Capcjc;
public
Modelica.Electrical.Analog.Interfaces.Pin C "Collector";
Modelica.Electrical.Analog.Interfaces.Pin B "Base";
Modelica.Electrical.Analog.Interfaces.Pin E "Emitter";
equation
ExMin = exp(EMin);
ExMax = exp(EMax);
vbc = B.v - C.v;
vbe = B.v - E.v;
qbk = 1 - vbc*Vak;
ibc = if (vbc/Vt < EMin) then Is*(ExMin*(vbc/Vt - EMin + 1) - 1) + vbc*
Gbc else if (vbc/Vt > EMax) then Is*(ExMax*(vbc/Vt - EMax + 1) - 1) +
vbc*Gbc else Is*(exp(vbc/Vt) - 1) + vbc*Gbc;
ibe = if (vbe/Vt < EMin) then Is*(ExMin*(vbe/Vt - EMin + 1) - 1) + vbe*
Gbe else if (vbe/Vt > EMax) then Is*(ExMax*(vbe/Vt - EMax + 1) - 1) +
vbe*Gbe else Is*(exp(vbe/Vt) - 1) + vbe*Gbe;
Capcjc = if (vbc/Phic > 0) then Cjc*(1 + Mc*vbc/Phic) else Cjc*pow(1 -
vbc/Phic, -Mc);
Capcje = if (vbe/Phie > 0) then Cje*(1 + Me*vbe/Phie) else Cje*pow(1 -
vbe/Phie, -Me);
cbc = if (vbc/Vt < EMin) then Taur*Is/Vt*ExMin*(vbc/Vt - EMin + 1) +
Capcjc else if (vbc/Vt > EMax) then Taur*Is/Vt*ExMax*(vbc/Vt - EMax + 1)
+ Capcjc else Taur*Is/Vt*exp(vbc/Vt) + Capcjc;
cbe = if (vbe/Vt < EMin) then Tauf*Is/Vt*ExMin*(vbe/Vt - EMin + 1) +
Capcje else if (vbe/Vt > EMax) then Tauf*Is/Vt*ExMax*(vbe/Vt - EMax + 1)
+ Capcje else Tauf*Is/Vt*exp(vbe/Vt) + Capcje;
C.i = (ibe - ibc)*qbk - ibc/Br - cbc*der(vbc) + Ccs*der(C.v);
B.i = ibe/Bf + ibc/Br + cbc*der(vbc) + cbe*der(vbe);
E.i = -B.i - C.i + Ccs*der(C.v);
end NPN;
Modelica.Electrical.Analog.Semiconductors.PNP
This model is a simple model of a bipolar pnp junction transistor according to Ebers-Moll.
A typical parameter set is:
Bf Br Is Vak Tauf Taur Ccs Cje Cjc Phie Me PHic Mc Gbc Gbe Vt - - A V s s F F F V - V - mS mS V 50 0.1 1e-16 0.02 0.12e-9 5e-9 1e-12 0.4e-12 0.5e-12 0.8 0.4 0.8 0.333 1e-15 1e-15 0.02585
| Name | Default | Description |
|---|---|---|
| Bf | 50 | Forward beta |
| Br | 0.1 | Reverse beta |
| Is | 1.e-16 | Transport saturation current [A] |
| Vak | 0.02 | Early voltage (inverse), 1/Volt [1/V] |
| Tauf | 0.12e-9 | Ideal forward transit time [s] |
| Taur | 5e-9 | Ideal reverse transit time [s] |
| Ccs | 1e-12 | Collector-substrat(ground) cap. [F] |
| Cje | 0.4e-12 | Base-emitter zero bias depletion cap. [F] |
| Cjc | 0.5e-12 | Base-coll. zero bias depletion cap. [F] |
| Phie | 0.8 | Base-emitter diffusion voltage [V] |
| Me | 0.4 | Base-emitter gradation exponent |
| Phic | 0.8 | Base-collector diffusion voltage [V] |
| Mc | 0.333 | Base-collector gradation exponent |
| Gbc | 1e-15 | Base-collector conductance [S] |
| Gbe | 1e-15 | Base-emitter conductance [S] |
| Vt | 0.02585 | Voltage equivalent of temperature [V] |
| EMin | -100 | if x < EMin, the exp(x) function is linearized |
| EMax | 40 | if x > EMax, the exp(x) function is linearized |
model PNP "Simple BJT according to Ebers-Moll"
parameter Real Bf=50 "Forward beta";
parameter Real Br=0.1 "Reverse beta";
parameter SIunits.Current Is=1.e-16 "Transport saturation current"
;
parameter SIunits.InversePotential Vak=0.02
"Early voltage (inverse), 1/Volt";
parameter SIunits.Time Tauf=0.12e-9 "Ideal forward transit time";
parameter SIunits.Time Taur=5e-9 "Ideal reverse transit time";
parameter SIunits.Capacitance Ccs=1e-12
"Collector-substrat(ground) cap.";
parameter SIunits.Capacitance Cje=0.4e-12
"Base-emitter zero bias depletion cap.";
parameter SIunits.Capacitance Cjc=0.5e-12
"Base-coll. zero bias depletion cap.";
parameter SIunits.Voltage Phie=0.8
"Base-emitter diffusion voltage";
parameter Real Me=0.4 "Base-emitter gradation exponent";
parameter SIunits.Voltage Phic=0.8
"Base-collector diffusion voltage";
parameter Real Mc=0.333 "Base-collector gradation exponent";
parameter SIunits.Conductance Gbc=1e-15
"Base-collector conductance";
parameter SIunits.Conductance Gbe=1e-15 "Base-emitter conductance"
;
parameter SIunits.Voltage Vt=0.02585
"Voltage equivalent of temperature";
parameter Real EMin=-100
"if x < EMin, the exp(x) function is linearized";
parameter Real EMax=40
"if x > EMax, the exp(x) function is linearized";
protected
Real vbc;
Real vbe;
Real qbk;
Real ibc;
Real ibe;
Real cbc;
Real cbe;
Real ExMin;
Real ExMax;
Real Capcje;
Real Capcjc;
public
Modelica.Electrical.Analog.Interfaces.Pin C "Collector";
Modelica.Electrical.Analog.Interfaces.Pin B "Base";
Modelica.Electrical.Analog.Interfaces.Pin E "Emitter";
equation
ExMin = exp(EMin);
ExMax = exp(EMax);
vbc = C.v - B.v;
vbe = E.v - B.v;
qbk = 1 - vbc*Vak;
ibc = if (vbc/Vt < EMin) then Is*(ExMin*(vbc/Vt - EMin + 1) - 1) + vbc*
Gbc else if (vbc/Vt > EMax) then Is*(ExMax*(vbc/Vt - EMax + 1) - 1) +
vbc*Gbc else Is*(exp(vbc/Vt) - 1) + vbc*Gbc;
ibe = if (vbe/Vt < EMin) then Is*(ExMin*(vbe/Vt - EMin + 1) - 1) + vbe*
Gbe else if (vbe/Vt > EMax) then Is*(ExMax*(vbe/Vt - EMax + 1) - 1) +
vbe*Gbe else Is*(exp(vbe/Vt) - 1) + vbe*Gbe;
Capcjc = if (vbc/Phic > 0) then Cjc*(1 + Mc*vbc/Phic) else Cjc*pow(1 -
vbc/Phic, -Mc);
Capcje = if (vbe/Phie > 0) then Cje*(1 + Me*vbe/Phie) else Cje*pow(1 -
vbe/Phie, -Me);
cbc = if (vbc/Vt < EMin) then Taur*Is/Vt*ExMin*(vbc/Vt - EMin + 1) +
Capcjc else if (vbc/Vt > EMax) then Taur*Is/Vt*ExMax*(vbc/Vt - EMax + 1)
+ Capcjc else Taur*Is/Vt*exp(vbc/Vt) + Capcjc;
cbe = if (vbe/Vt < EMin) then Tauf*Is/Vt*ExMin*(vbe/Vt - EMin + 1) +
Capcje else if (vbe/Vt > EMax) then Tauf*Is/Vt*ExMax*(vbe/Vt - EMax + 1)
+ Capcje else Tauf*Is/Vt*exp(vbe/Vt) + Capcje;
C.i = -((ibe - ibc)*qbk - ibc/Br - cbc*der(vbc) + Ccs*der(C.v));
B.i = -(ibe/Bf + ibc/Br + cbe*der(vbe) + cbc*der(vbc));
E.i = -B.i - C.i - Ccs*der(C.v);
end PNP;