Peng, Z. (1995). High-Level Test Synthesis Using Design Transformations. Technical Report LiTH-IDA-R-95-35, Department of Computer and Information Science, Linköping University, Sweden. (bibtex),
Abstract: A transformation-based approach to high-level test synthesis is presented. It utilizes a sequence of design-improvement transformations to generate a register-transfer level design from a VHDL behavioral specification. Selection of transformations is based on a performance-driven optimization strategy as well as a testability analysis algorithm which determines the testability-improvement techniques to be used. The main testability-improvement techniques are controllability/observability balance allocation, partial scan insertion and condition scan insertion. One important feature of our approach is that the testability-improvement trans-formations are not carried out in a separate synthesis step. Instead they are performed at the same time when operation scheduling, data path allocation and control allocation are carried out.
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