Eles, P., Kuchcinski, K., Peng, Z., and Doboli, A. (1994). Specification of Timing Constraints in VHDL for High-Level Synthesis. Technical Report LiTH-IDA-R-94-37, Department of Computer and Information Science, Linköping University, Sweden. (bibtex),
Abstract: This paper deals with the problem of timing constraint specification in VHDL for high-level synthesis purposes. We first discuss some possible approaches and define the basic requirements for a notation. According to these requirements a notation based on predefined subprograms is proposed for the specification of constraints on sequences of statements. The notation accepts nested timing constraints with specification of minimum, maximum, range, and exact limits and supports back-annotation for postsynthesis simulation. We have also provided support for specification of timing constraints across process borders. The mechanism is based on the concurrent assert statement and allows specification of timing constraints on signal events. One of the major problems discussed in the paper is consistency between the behavior of the simulation model and the synthesized hardware. We identify solutions to this problem in the frame of our two synthesis strategies and show in the paper how simulation/synthesis correspondence can be achieved for VHDL specifications containing both interacting processes and timing constraints.
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