Eles, P., Kuchcinski, K., Peng, Z., and Doboli, A. (1994). Back-Annotation of VHDL Behavioral Models for Postsynthesis Simulation. Technical Report LiTH-IDA-R-94-36, Department of Computer and Information Science, Linköping University, Sweden. (bibtex),
Abstract: The paper presents an approach to back-annotation of VHDL specifications containing time- constraints, for postsynthesis behavioral simulation. As a distinct feature, the mechanism does not rely on the well-timed assumption. This corresponds to the synthesis strategy adopted by the CAMAD system: different execution times can be synthesized for the alternative paths through a constrained statement sequence, with the restriction that all these times are consistent with the user specified timing requirements. Thus, our back-annotation strategy solves the tracing of the actual path run through a time-constrained sequence and the dynamic selection of the respective synthesized time for simulation. The actual time is selected during simulation using the dynamically constructed pattern that corresponds to the executed path. The elaborated algorithms are illustrated in the paper by some examples.
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