IDA Dept. of Computer and Information science, Linköping University

IDA Technical Reports: abstract

Generated: Mon, 19 Feb 2018 21:04:37

Eles, P., Kuchcinski, K., Peng, Z., and Minea, M. (1993). Two Methods for Synthesizing VHDL Concurrent Processes. Technical Report LiTH-IDA-R-93-22, Department of Computer and Information Science, Linköping University, Sweden. (bibtex),

Abstract: This paper presents two methods for high-level synthesis of VHDL specifications containing concurrent processes, that were implemented in the CAMAD high-level synthesis system. Our synthesis subset, called S'VHDL, accepts a large subset of standard VHDL including the concurrent features of the language. A primary concern was to preserve simulation/synthesis correspondence during synthesis and to produce hardware that operates at high performance with low complexity. One of the main difficulties lies in the fact that signal assignment semantics is defined in standard VHDL in terms of the simulation cycle. We first developed a method that allows a practically unrestricted use of signals and wait statements, by producing a synchronous hardware with a global control of process synchronization for signal update. The resulted hardware can be controlled either by a single state machine or by a collection of FSMs working synchronously together. The second method allows hardware synthesis without the strong synchronization imposed by the VHDL simulation cycle, by preserving at the same time simulation/synthesis correspondence. S'VHDL descriptions written according to the style accepted by this method are synthesized to asynchronously operating FSMs. We present in the paper the internal representation and solutions for synthesis according to both methods, as well as results obtained with the CAMAD system

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