Eles, P., Kuchcinski, K., Peng, Z., and Minea, M. (1992). Compiling VHDL into a High-Level Synthesis Design Representation. Technical Report LiTH-IDA-R-92-04, Department of Computer and Information Science, Linköping University, Sweden. Also has been accepted for presentation at the EURO-DAC ( EURO- Design Automation Conference), Hamburg, Germany, September 7-10, 1992. Was selected as the Best Paper of the EURO-DAC/VHDL conference in Hamburg, Germany. (bibtex),
Abstract: The paper discusses the problem of extending the use of VHDL to the field of hardware synthesis.The main difficulty lies in the fact that the semantics of standard VHDL is defined strictly in terms of simulation. We present a synthesis-oriented compiler based on a broad subset of VHDL. We describe the language subset, the internal design representation (based on an extended timed Petri net model), and the implementation of the front end as part of the CAMAD Synthesis System. Based on the fact that CAMAD supports the design of hardware with concurrency and asynchrony, our VHDL subset includes the concurrent features of the language. We state some important conclusions concerning how to deal with signals, wait statements, structured data, subprograms, from the specific point of view of synthesis. We discuss also the aspects of VHDL semantics that are strictly simulation oriented and should be redefined or ignored when dealing with synthesis.
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