Ubar, R., Kuchcinski, K., and Peng, Z. (1990). Test Generation for Digital Systems at Functional Level. Technical Report LiTH-IDA-R-90-06, Department of Computer and Information Science, Linköping University, Sweden. Also presented at the European Test Conference, Munich, April 10-12, 1991. (bibtex),
Abstract: This paper describes a test generation method to be used at the functional level of digital VLSI systems. Our major objective is to integrate the test generation problem into a more general framework of VLSI CAD system so that the test generation results can be used also to guide design transformations. A digital system design in this CAD system is described by an extended timed Petri net notation which allow different design trade-offs to be made so as to meet certain design requirements. This design representation is transformed into alternative graphs which capture the functionality of the design. A test generation algorithm will then be used to generate a set of tests. The main feature of the algorithm is that it deals with both the control flow and the data part of designs at register-transfer level. Our approach supports also hierarchical decomposition of digital systems, which can be used to improve the quality of test generation whenever needed.
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