Kuchcinski, K. and Peng, Z. (1989). Testability Analysis in a VLSI High-Level Synthesis System. Technical Report LiTH-IDA-R-89-42, Department of Computer and Information Science, Linköping University, Sweden. Also presented at the15th Symposium on Microprocessing and Microprogramming, EUROMICRO'89, Cologne, West Germany, September 4-8, 1989 and will be published in Microprocessing and Microprogramming, The EUROMICRO Journal, 1990. (bibtex),
Abstract: This paper deals with the problem of defining testability measures for register-transfer level designs in order to incorporate them into the high-level synthesis system of VLSI circuits. First, a design representation and its observability and controllability measures are defined. Second, an algorithm for testability analysis is described. Third, some discussion about how the testability measures can be used to influence the synthesis process is given. Finally, some practical impact and applications of the presented approach are also indicated.
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