Scheduling with Bus Access Optimization for Distributed Embedded Systems
IEEE Transactions on VLSI Systems, vol. 8, No 5, 472-491, October 2000.
In this paper we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application specific hardware components. The approach is based on an abstract graph representation which captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible, to generate a logically and temporally deterministic schedule, and optimize parameters of the communication protocol, such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only have particularities of the underlying architecture to be considered during scheduling, but the parameters of the communication protocol should also be adapted to fit the particular embedded application. The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.
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[EDPP00] Petru Eles, Alex Doboli, Paul Pop, Zebo Peng, "Scheduling with Bus Access Optimization for Distributed Embedded Systems", IEEE Transactions on VLSI Systems, vol. 8, No 5, 472-491, October 2000.