Assignment 3: Superscalar Processors
Table of Contents
Objective
The purpose of this assignment is to get insight on what
superscalarity means, how instructions are issued and scheduled in the
pipelines, how pipeline bubbles appear.
Time Allocation
4 hours (2 lab sessions) are allocated for this lab.
Theoretical Background
You should review one of the folowing resources before
you start working on this lab:
Assignments
You will
-
Choose a benchmark program
p from the
˜TDTS55/spec95-big subdirectory.
-
Trace the execution of approximately 30 instructions of
p
using sim-outorder with the initial superscalar
architecture specified in src/superscalar.cfg file.
-
Look into the trace file using
pipeview.pl <trace_file>.
Observe which stages are underused.
-
Perform several successive architectural modifications of the superscalar
processor with the goal to reduce the complexity of the architecture
while still keeping approximately the same performance for your benchmark
(e.g. the number of total simulation cycles should not increase more than 5%).
See below which are the allowed architectural modifications. For each
modification, retrace the same instructions and explain the trace
differences, if any. Explain the rationale behind your modifications.
Details:
Run sim-outorder -h for an explanation of its command
line switches and also read Section 4.4 from The
SimpleScalar Tool Set, Version 2.0, D. Burger, T. M. Austin. SimpleScalar
Hacker's Guide, T. Austin, could be helpful too.
In order to generate and view a trace, please read Section 5.1 from the same
user's guide.
You may modify the following architectural characteristics:
-
-fetch:speed (allowed range: 1-4)
-
-decode:width (allowed range: 1-16)
-
-issue:width (allowed range: 1-8)
-
-commit:width (allowed range: 1-8)
-
-ruu:size (allowed range: 1-32)
-
-res:ialu (allowed range: 1-4)
-
-res:imult (allowed range: 1-4)
-
-res:fpalu (allowed range: 1-2)
-
-res:fpmult (allowed range: 1-2)
What to hand-in
-
Indicate the chosen program and the instructions you traced.
-
A description of the modification you performed. Describe the
rationale behind them. Indicate the impact of the modifications on the
traces. Explain in detail why the traces changed ("because I modified
the architecture" is not a good enough answer).
Resources